Abstract: A system and method are provided which include devices implementing a snooping protocol. Data to be written by an I/O peripheral to an I/O controller is mapped to a specific location in memory, and then the data is actually written to an L1 cache in the controller by the I/O device. During this period when the I/O device is writing to the controller cache, the controller does not actually own the data stored in the specific memory location. Once the write operation is complete for a given memory sector, the I/O controller then performs the bus operations required to obtain ownership of the data in the specified memory location. The data read from memory is then merged with the data written from the I/O device and written back to the memory. If a snoop hit is identified by the I/O controller, during the period when the data is owned the I/O controller intervenes to prevent the memory access which caused the snoop hit.

Abstract: A system and method dynamically changes the snoop comparison granularity between a sector and a page, depending upon the state (active or inactive) of a direct memory access (DMA) I/O device which is writing to a device on the system bus asynchronously when compared to the CPU clock. By using page address granularity, erroneous snoop hits will not occur, since potentially invalid sector addresses are not used during the snoop comparison. Sector memory addresses may be in a transition state at the time when the CPU clock determines a snoop comparison is to occur, because this sector address has been requested by a device operating asynchronously with the CPU clock. Once the asynchronous device becomes inactive the system dynamically returns to a page and sector address snoop comparison granularity.

Abstract: A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.