Abstract: In concentrated multiprocessor systems conforming to the presently disclosed modular architecture, a host processor and plural client processors are packaged in a single box containing a high speed (short length) bus connecting all of the processors, and data storage resources via the bus. The bus may be of a type commonly used in contemporary single computer systems; e.g. one conforming to PCI specifications. The host processor and associated resources are mounted directly on an integrated circuit motherboard containing the bus and card connectors attached to the bus. The card connectors removably receive integrated circuit cards containing individual client processors. In one embodiment, client processors are configured to be used as workstations or PC's—in a residence, office or small factory environment—relative to users and accessories remote from the system enclosure.

Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.c and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo N.sub.c combinational ring shifter for aligning the data field with the data bus.

Abstract: A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer connected in between the first and second bit arrays on each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A controller is located on each chip and connected to the first and second memory arrays and the M bit buffer for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.