Abstract: Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown topology and a plurality of unknown devices. The methods use set and get configuration commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

Abstract: An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.

Abstract: A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link (110), such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device (120) coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Abstract: Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

Abstract: An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.

Abstract: An asynchronous FIFO is provided that determines whether its buffer is primed with at least one data element during a data transfer across clock domains in order to eliminate metastability issues that cause data stalls and interruptions in data flow.

Abstract: A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Abstract: A method of indicating data availability is disclosed. According to the method a data read operation is commenced for retrieving data signals based on data stored within an SDRAM. The data is provided from the SDRAM device with a first propagation delay. The SDRAM device also provides a strobe signal having a propagation delay similar to the first propagation delay. Based on the strobe signal data is latched out of the SDRAM device, as it is available to be read.

Abstract: A method of indicating data availability is disclosed. According to the method a data read operation is commenced for retrieving data signals based on data stored within an SDRAM. The data is provided from the SDRAM device with a first propagation delay. The SDRAM device also provides a strobe signal having a propagation delay similar to the first propagation delay. Based on the strobe signal data is latched out of the SDRAM device, as it is available to be read.

Abstract: A computer system with a multi-master system bus includes a memory controller that changes the burst mode of the including memory system automatically as a function of the selected master. The controller includes a programmable look-up table into which is stored a value B corresponding to a fixed memory burst mode; for each master, a multiplier is stored indicating the multiple of the burst mode that would be optimal for that master. The grant signal used to select the current master is also used to select the multiplier M associated with that master. In response to a read request by the current master, a requested address is forwarded to the memory. Then the controller generates and transmits M−1 addresses spaced B addresses apart every Bth bus cycle. This implements a memory system burst of M*B addresses with no latencies between successive B-address memory bursts. The memory system burst can be aborted if an address in the burst is not confirmed by a subsequent address request by the master.