Patents by Inventor Dennis Mazur

Dennis Mazur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230372181
    Abstract: A motorized cervical traction device comprises an inferior base configured to attach to a patient support (such as an operating table or gurney), a superior base spaced apart from the inferior base along a cranial/caudal direction, and a set of linear actuators extending between the inferior base and the superior base. The superior base includes an attachment point configured to enable mechanical coupling of a load sensor and a patient head attachment (e.g., Gardner-Wells device or Mayfield skull clamp) to the superior base. In use, the device provides real-time load sensing capability and can apply distraction via extension of the linear actuators to a preset load (force control) or displacement (position control). The device also includes a flexion/extension mechanism that enables rotational positioning of the linear actuators relative to the inferior base along and enables control of the flexion/extension angle of the applied traction.
    Type: Application
    Filed: February 24, 2023
    Publication date: November 23, 2023
    Inventors: Brandon A. SHERROD, Trevor SCHWEHR, Andrew ADAMS, Sterling AVERETT, Jeewon HA, Simon KAHLE, Derek MITCHELL, Seth POLEVOI, Andrew MERRYWEATHER, Marcus Dennis MAZUR
  • Patent number: 7852781
    Abstract: Communications settings are managed. System characteristics are determined that affect communications on a high speed transmission link between nodes. The system characteristics includes system hardware information and physical characteristics of a cable. Tuning information is derived from the system characteristics. At least some of the tuning information is communicated between the nodes.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 14, 2010
    Assignee: EMC Corporation
    Inventors: Mickey Steven Felton, Thomas Dibb, Dennis Mazur, Steven D. Sardella, Bernard Warnakulasooriya
  • Patent number: 7380174
    Abstract: Embodiments include writing a first data value to a validation variable through a fixed programming interface, where the validation variable includes multiple fields that correspond to multiple fields within a persistent variable. Contents of the validation variable are subsequently read through the fixed programming interface. When the validation variable contents include one or more differences from the first data value, one or more errors are identified.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: May 27, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David T. Mayo, Bradley G. Culter, Dennis Mazur
  • Publication number: 20060075309
    Abstract: Embodiments include writing a first data value to a validation variable through a fixed programming interface, where the validation variable includes multiple fields that correspond to multiple fields within a persistent variable. Contents of the validation variable are subsequently read through the fixed programming interface. When the validation variable contents include one or more differences from the first data value, one or more errors are identified.
    Type: Application
    Filed: September 28, 2004
    Publication date: April 6, 2006
    Inventors: David Mayo, Bradley Culter, Dennis Mazur
  • Patent number: 6973517
    Abstract: The invention is a control system using microprocessors which communicate through a Local Area Network (private LAN) to control operation of both processors and input and output subsystems (IO system) of a multiprocessor computer system. The processors each have memory associated therewith, and each processor has an IO system comprising a plurality of busses such as PCI busses, associated therewith. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or delivered to an IO system associated with the destination processor, etc.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 6, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Golden, Dennis Mazur, Richard Edward Bracken
  • Patent number: 5255367
    Abstract: A dual processor computer system includes a first processing system having a central processing unit which executes a series of data processing instructions, a data bus system for transferring data to and from the first central processing unit, a memory unit coupled to the first central processing unit, and a cross-link communications element for transferring data into and out of the first processing system. A similarly configured second processing system, operating independently of the first processing system, is also provided. The cross-link communications element associated with the second processing system is coupled to the cross-link communication element of the first processing system, for transferring data into the second processing system from the first processing system and for transferring data into the first processing system from the second computer system.
    Type: Grant
    Filed: July 19, 1989
    Date of Patent: October 19, 1993
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Thomas D. Bissett, Dennis Mazur, John Munzer
  • Patent number: 5099485
    Abstract: A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.
    Type: Grant
    Filed: May 25, 1989
    Date of Patent: March 24, 1992
    Assignee: Digital Equipment Corporation
    Inventors: William F. Bruckert, Thomas D. Bissett, Dennis Mazur, John Munzer, Frank Bernaby, Jay H. Bhatia
  • Patent number: 5068780
    Abstract: Method and apparatus for controlling initiating of bootstrap loading in a computer system having first and second discrete computing zones is disclosed. Each computing zone includes a status register for storing an operating system run (OSR) bit indicating that the zone has initiated bootstrap loading. A cable connects the computing zones to allow the first and second zones to read the status registers in the second and first zones, respectively. A CPU in each zone only enables initiation of bootstrap loading if the OSR bit in the other zone is not set.
    Type: Grant
    Filed: August 1, 1989
    Date of Patent: November 26, 1991
    Assignee: Digital Equipment Corporation
    Inventors: William Bruckert, David Kovalcin, Thomas D. Bissett, John Munzer, Dennis Mazur, Peter R. Mott, Jr., Glenn A. Dearth, Carlos Alonso, Ann Katan