Abstract: A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

Abstract: A novel cable clip for retainment of cables or tubing which utilizes a one-piece J-shaped rigid body (9) comprising of a cupped shaped bottom (10) having both ends open, a short side (11) having a locking device located at the end of the said short side (11), a long side (12) having a locking device located at the unattached end of the punched-out projection surface (13), said punched-out projection surface extending in a downward direction pointing towards the said short side locking device and being part of said long side (12). At the upper end of said long side (12) having an attachment hole (14) having a mechanical device for attachment of said J-shaped rigid body (9) to a substructure. The said J-shaped rigid body (9) can be flexed repeatedly along the surface of both the short side (11 ) and long side (12) where they become common with the cupped shaped bottom (10) without fracturing, allowing the locking devices to interlock repeatedly and to disengage repeatedly.

Abstract: A method and apparatus for reducing the effective latency for nonsequential memory accesses is disclosed. An improved cache includes a multi-stage pipelined cache that provides at least one cache output record in response to a record address hitting the pipelined cache. The pipelined cache provides the record after an idle period of L clock cycles in which the pipelined cache provides no output records. The effective latency of the pipelined cache is reduced by providing a branch target cache (BTC) that issues at least one record during the idle period in response to a nonsequential record address hitting the BTC. The records stored in the caches may, for example, represent instructions. The cache further includes a lookahead circuit for providing the nonsequential record address (A) and a lookahead address (A+(L.times.W), where W denotes the issue width) to the pipelined cache during a zero cycle preceding the idle period.