Abstract: This invention provides apparatus and methods for causing a fluorescent lamp drive circuit to provide a continuous drive signal over a first (high) range of lamp intensity, and a pulse width modulated (PWM) drive signal over a second (low) range of lamp intensity, with a smooth transition between continuous and PWM drive that is unnoticeable to the user. This invention also provides fluorescent lamp circuits that include lamp intensity control circuitry, fluorescent lamp drive circuitry and a fluorescent lamp, the lamp intensity control circuitry providing control signals that cause the fluorescent lamp drive circuit to provide a continuous drive signal over a first (high) range of lamp intensity, and a PWM drive signal over a second (low) range of lamp intensity, with a smooth transition between continuous and PWM drive that is unnoticeable to the user.

Abstract: An error amplifier circuit is provided having a pair of current mirror transistors driven by a pair of current sources, where one of the current mirror transistors operates at a lower current density than the other, and further having a resistor in an emitter circuit of the transistor operating at the lower current density and a summing node in the emitter circuit between the emitter of the one transistor and the resistor. A feedback circuit including a second resistor and a base-emitter circuit of a third transistor is in series between a feedback node coupled to the base of the feedback transistor and the summing node, such that a current from the feedback circuit is summed with the current conducted by the emitter of the one transistor. The error amplifier is balanced when the voltage at the feedback node is equal to a predetermined voltage, which can have substantially zero temperature coefficient at a voltage as low as one bandgap voltage.

Abstract: A bias generator circuit having a zero-current shutdown state is provided. When on, the bias generator circuit provides substantially constant bias currents (sourcing and/or sinking) and may be selectively turned on and off in response to first and second control signals. When the bias generator is off, it is in a zero-current shutdown state such that substantially no quiescent current is used.

Abstract: Efficient very low dropout (i.e., approximately equal to about V.sub.CESAT of the output transistor) dual supply voltage regulator circuits and methods are provided. The voltage regulators are capable of providing very low dropout irrespective of supply sequencing. Traditional supply sequencing problems are overcome by including an power-on circuit that monitors the output power supply during power-on. The power-on circuit is also coupled to any location in the regulator circuit where the drive current can be inhibited whenever the output power monitor senses that the output power supply is not fully operational. The power-on circuit operates to prevent drive current from being supplied to the output transistor unless output power is available so that the substrate of the regulator is not permitted to become forward biased (and thus prevents the establishment of an undesired latch condition).

Abstract: Efficient very low dropout (i.e., approximately equal to about V.sub.CESAT of the output transistor) dual supply voltage regulator circuits and methods are provided. The voltage regulators are capable of providing very low dropout irrespective of supply sequencing. Traditional supply sequencing problems are overcome by including an anti-latch circuit that monitors the output power supply during power-on. The anti-latch circuit is also coupled to any location in the regulator circuit where the drive current can be inhibited whenever the output power monitor senses that the output power supply is not fully operational. The anti-latch circuit operates to prevent drive current from being supplied to the output transistor unless output power is available so that the substrate of the regulator is not permitted to become forward biased (and thus prevents the establishment of an undesired latch condition).

Abstract: A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base-drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

Abstract: A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

Abstract: A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

Abstract: An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on.

Abstract: A current limit circuit is provided which may be used to limit the current conducted by a pass transistor in a low dropout voltage regulator circuit having no ground terminal. The output current of the regulator is sensed by a low value resistor in the collector of the transistor. The voltage developed across the resistor is proportional to the output current of the regulator, and is used to vary a current ratio which sets the current limit value. The gain of the current limit loop is increased by providing positive feedback during current limiting. A foldback network is provided which reduces the current limit value at higher input/output voltage differentials. The feedback provided by the foldback network has a breakpoint which is sensitive to the operating temperature of the regulator circuit.

Abstract: A circuit is provided for reducing the turn-off transition time of a switching PNP transistor by providing a reverse drive current to the base of the PNP transistor after the drive current has been removed from the base. The reverse drive current is generated by an NPN transistor, the emitter of which is connected to the base of the PNP transistor. A capacitor coupled to the base of the NPN transistor is charged and during the conducting period of the PNP transistor and discharged after the drive current is removed from the base of the PNP transistor to enable the base of the NPN transistor to be driven above the supply voltage connected to the emitter of the PNP transistor.

Abstract: A push-pull circuit in which an output terminal is alternately connected to first and second voltage potentials through first and second bipolar transistors, first biasing circuitry is provided for controlling the conductance of the first transistor with the first biasing circuitry being responsive to the base/emitter voltage of the second transistor whereby the first transistor cannot be biased on while the second transistor is conductive, and biasing circuitry is provided for the second transistor with the second bias circuitry being responsive to base/emitter voltage of the first transistor whereby the second transistor cannot be biased on while the first transistor is conductive.

Abstract: A bias control loop forms a voltage regulator for providing the bias voltage to the collectors of bipolar current source transistors in a linear circuit. The bias loop functions by maintaining equal or related base/emitter voltages on the several transistors. By properly sizing the emitter areas of the transistors, interrelated voltages and transistor biases are provided in the loop. The bias loop works down to less than 1 volt and is stable without a compensation capacitor.