Abstract: An SRAM memory cell made with increased stability using SOI technology is provided. Increased stability occurs because of raising the threshold voltage of the transfer nfets connected to the word line. Preferably the increase of threshold voltage is achieved using boron ion implantation.

Abstract: A method and system in a data processing system for providing a dual-port memory device having redundant data stored in multiple memory arrays. A first set of data and address latches, coupled to a first data port, are provided for storing data and address information. A second set of data and address latches, coupled to a second data port, are provided for storing data and address information. Each data port is coupled to a memory array. After an external memory access period, a cross-write circuit performs an internal cross-write operation by writing data into a second memory array in response to data previously written to a first memory array and stored in the first set of data and address latches, and writing data into a first memory array in response to data previously written to a second memory array and stored in the second set of data and address latches, wherein a redundant copy of data written to either the first or second memory arrays is created.

Abstract: A performance-sensing element (PSE) circuit detects the actual speed of other circuits on the same chip by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.

Abstract: A circuit macro is provided for a VLSI circuit device having a semiconductor substrate and M1 and M2 metal layers defining a grid of M1 and M2 conductive lines extending in orthogonal directions. Numerous similar unit cells are arrayed side-by-side in rows extending in one direction and each unit cell spans an integral number of M1 conductive lines and an integral number of M2 conductive lines. The circuit device includes a plurality of circuit blocks each including two of the rows of unit cells. A plurality of wiring bays extend between adjacent circuit blocks, and each wiring bay includes a plurality of M1 conductive lines. The circuit macro includes a number of circuti blocks separated by wiring bays, and connections extend to unit cells of circuit blocks included in the macro.

Abstract: This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

Abstract: This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic performed on the variables fed to the other end.The arrays are compounded. Two arrays are arranged on opposite sides of a third array and the output signals from the two arrays function as input variables to the third array. Input lines in the third array can also be broken to separate array logic functions performed in the third array on variables fed to the opposite ends of such lines.

Abstract: This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays are selectively connected to individual rails so that the rails carry the input signals to the arrays from off the chip and take output signals of the arrays off the chip and to inputs of the arrays. The rails are selectively segmented so that each segment of a rail may be used as a path for an input and/or output signal without interfering with signals on other segments of the same rail.