Patents by Inventor Dennis W. Brzezinski

Dennis W. Brzezinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7761753
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
  • Patent number: 7734980
    Abstract: Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventors: James W. Alexander, Suresh Chittor, Dennis W. Brzezinski, Kai Cheng, Rajat Agarwal
  • Patent number: 7644347
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: James W. Alexander, Suresh Chittor, Dennis W. Brzezinski, Kai Cheng, Henk Neefs, Rajat Agarwal
  • Publication number: 20090319877
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame.
    Type: Application
    Filed: June 18, 2008
    Publication date: December 24, 2009
    Inventors: Kuljit S. Bains, Dennis W. Brzezinski
  • Publication number: 20090013211
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Application
    Filed: June 9, 2008
    Publication date: January 8, 2009
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
  • Patent number: 7386768
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
  • Publication number: 20040250181
    Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
    Type: Application
    Filed: June 5, 2003
    Publication date: December 9, 2004
    Applicant: Intel Corporation
    Inventors: Pete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow