Abstract: An animal release chute for use in steer or calf roping competitions is described. The chute has a fixed section and a moveable section that telescopes forwardly relative to the fixed section. A release gate at the forward end of the moveable section is moveable between a closed position for retaining a steer or calf inside the chute and an open position releasing the steer or calf from the chute. A sensor at the rearward end of the fixed section senses the presence of the horse of the roper at the rearward end of the fixed section. Only when the roper's horse is at the rearward end of the fixed section can the gate be released to release the calf. The chute system assures that there is always the fixed, predetermined distance between the calf and the roper at release.

Abstract: A number of storage units and a number of state machines are provided to reorder interleaved ATM data cells for a number of channels incoming to a networked host computer. The storage units store the incoming ATM data cells, a number of data structures tracking the stored ATM data cells for the channels and the free resources, and an unload schedule queue. The state machines load and unload the incoming ATM data cells, and update the tracking data structures and schedule queue accordingly.

Abstract: A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ("TX") DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common the overhead information for the block of data to avoid the TX DMA engine re-accessing the data descriptor to obtain the same overhead information for each frame being transferred.