Abstract: A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.