Abstract: An anechoic chamber and a construction method thereof are provided, the anechoic chamber includes a top surface, being a polygon; trapezoid surfaces, corresponding to edges of top surface, upper edge lengths of trapezoid surface being equal to edge lengths of top surface, trapezoid surfaces being connected to edges of top surface through the upper edges, the trapezoid surfaces being sequentially connected along a circumferential direction of top surface, and being at angle to the top surface; rectangular surfaces, corresponding to the trapezoid surfaces, upper edge lengths of rectangular surface being equal to lower edge lengths of trapezoid surface, rectangular surfaces being connected to the trapezoid surfaces through the upper edges, the rectangular surfaces being sequentially connected along a circumferential direction of the lower edges of trapezoid surfaces, and being perpendicular to the top surface; and an absorbing material, disposed on the top surface, the trapezoid surfaces and the rectangular surf

Abstract: An anechoic chamber and a construction method thereof are provided, the anechoic chamber includes a top surface, being a polygon; trapezoid surfaces, corresponding to edges of top surface, upper edge lengths of trapezoid surface being equal to edge lengths of top surface, trapezoid surfaces being connected to edges of top surface through the upper edges, the trapezoid surfaces being sequentially connected along a circumferential direction of top surface, and being at angle to the top surface; rectangular surfaces, corresponding to the trapezoid surfaces, upper edge lengths of rectangular surface being equal to lower edge lengths of trapezoid surface, rectangular surfaces being connected to the trapezoid surfaces through the upper edges, the rectangular surfaces being sequentially connected along a circumferential direction of the lower edges of trapezoid surfaces, and being perpendicular to the top surface; and an absorbing material, disposed on the top surface, the trapezoid surfaces and the rectangular surf

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

Abstract: In one aspect, a VCO is provided. The VCO includes an inductor, a voltage-controlled capacitive element configured to operate with the inductor to generate an oscillating signal, a voltage supply configured to provide a plurality of voltages to the voltage-controlled capacitive element in a calibration mode, and a control circuit configured to store frequency information indicating frequencies of the oscillating signal in response to the plurality of voltages being provided to the voltage-controlled capacitive element. In another aspect, a PLL is provided. The PLL includes means for selecting, in an open loop configuration, a capacitance of a capacitor based on a target frequency and means for selecting, in a closed loop configuration, an operation voltage of a voltage-controlled capacitive element based on the capacitance of the capacitor.

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(?1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract: Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(?1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract: In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(?1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract: This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Abstract: A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

Abstract: In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(?1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

Abstract: A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.