Patents by Inventor Der-Ling Hsia
Der-Ling Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160380173Abstract: A light emitting device manufacturing method includes the following steps. A sub-mount, which has a plurality of electrical-conductive layers, is provided, and a surface between every adjacent two of the electrical-conductive layers has an adhesive-filling groove. An LED chip, which has a bottom substrate, is mounted on the sub-mount by a flip-chip way, and two electrodes of the LED chip are in contact with adjacent two of the electrical-conductive layers. Glue is filled along the adhesive-filling groove to be guided into a gap between the LED chip and the sub-mount.Type: ApplicationFiled: September 8, 2016Publication date: December 29, 2016Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Patent number: 9461213Abstract: A LED sub-mount includes a substrate body and a plurality of first electrical-conductive layers. The substrate body has a first surface. The first electrical-conductive layers are positioned on the first surface of the substrate body, wherein the first surface between every adjacent two of the first electrical-conductive layers has an adhesive-filling groove.Type: GrantFiled: February 7, 2014Date of Patent: October 4, 2016Assignee: Lextar Electronics CorporationInventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Publication number: 20150034959Abstract: A light emitting diode structure includes a patterned substrate, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer. Plural protruding portions are formed on a surface of the substrate. A horizontal projection of each of the protruding portions on the surface of the substrate has a projection width W1. An interval width W2 is formed between every two adjacent protruding portions. A vertical height h is formed between a peak of each of the protruding portions and the horizontal surface of the surface of the substrate. The value of {[(W1)/2+W2]/h} is substantially equal to tan 46°. The N-type semiconductor layer is located on the substrate and covers the protruding portions. The light emitting layer is located on the N-type semiconductor layer. The P-type semiconductor layer is located on the light emitting layer.Type: ApplicationFiled: April 7, 2014Publication date: February 5, 2015Applicant: Lextar Electronics CorporationInventors: Yi-Ju CHEN, Der-Ling HSIA, Chih-Wei CHAO, Cheng-Ta KUO
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Publication number: 20140231858Abstract: A LED sub-mount includes a substrate body and a plurality of first electrical-conductive layers. The substrate body has a first surface. The first electrical-conductive layers are positioned on the first surface of the substrate body, wherein the first surface between every adjacent two of the first electrical-conductive layers has an adhesive-filling groove.Type: ApplicationFiled: February 7, 2014Publication date: August 21, 2014Applicant: Lextar Electronics CorporationInventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Patent number: 8445327Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.Type: GrantFiled: February 23, 2012Date of Patent: May 21, 2013Assignee: Lextar Electronics Corp.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Patent number: 8415683Abstract: The present invention provides a manufacturing method of an LED chip. First, a device layer is formed on a growth substrate, wherein the device layer has a first surface connected to the growth substrate and a second surface. Next, a plurality of first trenches are formed on the second surface of the device layer. Then, a protection layer is formed on the side walls of the first trenches. After that, the second surface is bonded with a supporting substrate and the device layer is then separated from the growth substrate. Further, a plurality of second trenches corresponding to the first trenches are formed in the device layer to form a plurality of LEDs, wherein the second trenches extend from the first surface to the bottom portions of the first trenches. Furthermore, a plurality of electrodes are formed on the first surface of the device layer.Type: GrantFiled: May 12, 2009Date of Patent: April 9, 2013Assignee: Lextar Electronics Corp.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Patent number: 8278681Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.Type: GrantFiled: May 20, 2009Date of Patent: October 2, 2012Assignee: Lextar Electronics Corp.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Publication number: 20120164768Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.Type: ApplicationFiled: February 23, 2012Publication date: June 28, 2012Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Publication number: 20100258827Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.Type: ApplicationFiled: May 20, 2009Publication date: October 14, 2010Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia
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Publication number: 20100258818Abstract: The present invention provides a manufacturing method of an LED chip. First, a device layer is formed on a growth substrate, wherein the device layer has a first surface connected to the growth substrate and a second surface. Next, a plurality of first trenches are formed on the second surface of the device layer. Then, a protection layer is formed on the side walls of the first trenches. After that, the second surface is bonded with a supporting substrate and the device layer is then separated from the growth substrate. Further, a plurality of second trenches corresponding to the first trenches are formed in the device layer to form a plurality of LEDs, wherein the second trenches extend from the first surface to the bottom portions of the first trenches. Furthermore, a plurality of electrodes are formed on the first surface of the device layer.Type: ApplicationFiled: May 12, 2009Publication date: October 14, 2010Applicant: LEXTAR ELECTRONICS CORP.Inventors: Chia-En Lee, Cheng-Ta Kuo, Der-Ling Hsia