Patents by Inventor Der-Shin Shyu
Der-Shin Shyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7557402Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.Type: GrantFiled: November 15, 2006Date of Patent: July 7, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Publication number: 20070063248Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.Type: ApplicationFiled: November 15, 2006Publication date: March 22, 2007Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Patent number: 7176083Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.Type: GrantFiled: June 17, 2004Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Publication number: 20060203537Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.Type: ApplicationFiled: March 11, 2005Publication date: September 14, 2006Inventors: Hung-Cheng Sung, Der-Shin Shyu
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Patent number: 7102919Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.Type: GrantFiled: March 11, 2005Date of Patent: September 5, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Cheng Sung, Der-Shin Shyu
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Patent number: 7056791Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.Type: GrantFiled: June 3, 2004Date of Patent: June 6, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang, Hsui Ouyang
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Publication number: 20050282337Abstract: An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.Type: ApplicationFiled: June 17, 2004Publication date: December 22, 2005Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Patent number: 6878986Abstract: A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.Type: GrantFiled: March 31, 2003Date of Patent: April 12, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Publication number: 20040248367Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.Type: ApplicationFiled: June 3, 2004Publication date: December 9, 2004Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang, Hsui Ouyang
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Patent number: 6819593Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.Type: GrantFiled: December 13, 2002Date of Patent: November 16, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Der-Shin Shyu, Hung-Cheng Sung, Li-Wen Chang, Han-Ping Chen, Chen-Ming Huang, Ya-Chen Kao
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Publication number: 20040188750Abstract: A memory cell including a substrate having a source region; a floating gate structure disposed over the substrate and associated with the source region; and a source coupling enhancement structure covering an exposed portion of the floating gate structure and extending to the source region. The flash memory cell can be fabricated in a method including the steps of forming the floating gate structure over a substrate; forming the source coupling enhancement structure on an exposed portion of the floating gate structure; and forming the source region in the substrate.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang
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Publication number: 20040114435Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Der-Shin Shyu, Hung-Cheng Sung, Li-Wen Chang, Han-Ping Chen, Chen-Ming Huang, Ya-Chen Kao
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Patent number: 6649489Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.Type: GrantFiled: February 13, 2003Date of Patent: November 18, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Li-Wen Chang, Hung-Cheng Sung, Der-Shin Shyu, Han-Ping Chen, Chen-Ming Huang, Ya-Chen Kao
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Patent number: 6569736Abstract: A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.Type: GrantFiled: February 14, 2002Date of Patent: May 27, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Cheng-Yuan Hsu, Hung-Cheng Sung, Su-Chang Chen, Han-Ping Chen, Chia-Ta Hsieh, Der-Shin Shyu
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Patent number: 6215697Abstract: A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell.Type: GrantFiled: January 14, 1999Date of Patent: April 10, 2001Assignee: Macronix International Co., Ltd.Inventors: Tao Cheng Lu, Der Shin Shyu, Shi Xian Chen, Wen Jer Tsai, Mam Tsung Wang