Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

Abstract: A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

Abstract: A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Abstract: A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

Abstract: A copper fuse structure and the method for fabricating the same is disclosed in this present invention. By employing an inner copper metal layer as a fuse, the copper fuse according to this invention can be easily zipped with a laser repair tool. Furthermore, the openings on a bonding pad and the fuse of the semiconductor structure can be identified with the method according to this invention. Moreover, in contrast of the fuse formed with an upper aluminum layer in the prior art, the cost of the fuse manufacturing is lower in the method according to this invention by fabricating the fuse with an inner copper layer.

Abstract: A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

Abstract: The present invention provides a method to manufacture a trench DRAM. The present method can avoid the latch-up phenomenon of a transistor, and can efficiently increase the ability of storing charge of a capacitor to avoid the soft errors caused by &agr; particles. In this method, an SOI is used to manufacture the trench DRAM. Because a dielectric layer in SOI separates the transistor from the substrate, the latch-up phenomenon can be avoided. By using oxygen-ion implantation, silicon layers can be divided, and elements can adequately be separated from each other.

Abstract: First of all, a semiconductor substrate is provided. On the semiconductor substrate, a word line is formed and covered with a insulating layer. Next, forming a connected device in the insulating layer to connect with the first conducting line layer. In order, a pinned layer is then deposited along the first insulating layer and the connected device. On top of the pinned layer, an insulating tunnel barrier layer is formed. Then a free layer is deposited on the insulating tunnel barrier layer. There is a single large MTJ that covers the entire surface of the first insulating layer on the conducting line layer. This large MTJ is then patterned into a small MTJ by etching process and through the free layer to the surface of the insulating tunnel barrier layer. Subsequently, the small MTJ are then covered with a second insulating layer. Afterward, opening a contact hole in the second insulating layer to the top of the small MTJ.

Abstract: A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate.

Abstract: First of all, a junction protecting layer are formed on the semiconductor substrate. The junction protecting layer is then etched to expose a partial surface of the semiconductor substrate as an opening. Next, a semiconductor layer is formed over the junction protecting layer to fill the opening. After forming a gate on the semiconductor layer, implanting the LDD in the semiconductor layer. Afterward, a spacer layer is conformed along the surfaces of the gate and the LDD. Subsequently, performing an etching process to etch through the spacer layer, the semiconductor layer, and the junction protecting layer until exposing the partial surfaces of the semiconductor substrate, so as to form the etched regions and a spacer beside each sidewall of the gate. Finally, the source/drain region is formed respectively in each etched region, after the etched regions are filled with the material the same with the substrate.

Abstract: A method for manufacturing a semiconductor device with a shallow channel on a silicon-on-insulator substrate is disclosed. The method uses a dielectric layer as a mask, an oxygen implantation and a heating process to form a silicon dioxide layer within a silicon-on-insulator substrate before forming a gate electrode on the silicon-on-insulator substrate. That is, the junction depth of the channel is reduced. First of all, a silicon-on-insulator substrate having a silicon layer and an insulating layer is provided, wherein the silicon layer is separated by the insulating layer. Secondly, a first dielectric layer is deposited on the silicon layer. Thirdly, a gate region pattern is transferred into the first dielectric layer to form a trench and expose the silicon layer. Then, oxygen molecules are implanted into the silicon layer, and the silicon-on-insulator substrate is heated to form a silicon dioxide layer therein. Next, a second dielectric layer is deposited and the trench is filled with the same.

Abstract: A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor and an interconnect in integrated circuits is provided. First, a substrate with a plurality of conductive blocks under a surface of substrate is provided. Then, a first nitride layer is deposited on the substrate and then a first inter-metal-dielectric (IMD) layer is formed thereon. Next, a second nitride layer and a second IMD layer are sequentially formed on the first IMD layer. Thereafter, a first mask is formed on the second IMD layer with a first opening to expose the second IMD layer. Next, a first etching process is performed to form a via through the second IMD layer, the second nitride layer, the first IMD layer and the first nitride layer in the first opening to expose one of those conductive blocks. Then, a second etching process is performed to form a hole to expose the first nitride layer, wherein the hole is above one of those conductive blocks.

Abstract: A method of fabricating an embedded dynamic random access memory. After a gate and a source/drain region are formed on a semiconductor substrate, an etch stop layer and a dielectric layer are sequentially formed. The dielectric layer is etched back and patterned, and only the dielectric layer over the source/drain region in the memory circuit region remain. The exposed etch stop layer is removed to expose the salicide layer on the gate and the source/drain region in the logic circuit region.

Abstract: The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

Abstract: A method is for forming a deep trench capacitor under a shallow trench isolation structure. The method first provides a substrate and sequentially forms a pad oxide, a first mask layer, and a second mask layer over the substrate. A photoresist layer formed on the second mask layer has a thicker portion and a thinner portion, location of the thinner portion is the predetermined location to be formed an STI structure thereunder. A photoresist opening is between the thicker portion and the thinner portion to form a deep trench in the substrate by etching. The photoresist layer is removed, wherein the second mask layer under the thinner portion of the photoresist layer is also removed to expose the first mask layer. A deep trench capacitor is formed on the lower portion of the deep trench. A dielectric collar layer is formed on the sidewall of the deep trench. A selective growth polysilicon layer is formed to fill the deep trench with a height higher than the substrate surface.

Abstract: A method of fabricating a salicide gate is provided, wherein a logic region and a memory cell region are formed on a substrate. A plurality of polysilicon gates and adjoining source/drain regions are also formed in both regions. A protection layer is formed to cover the polysilicon gates and the source/drain regions, followed by forming a photoresist layer on the substrate. A blanket defocus exposure is then conducted, whereby a part of the protection layer on the top surface of the polysilicon gates in both regions is eventually removed. Another photoresist layer is formed in the memory cell region, while the protection layer in the logic region is removed. A self-aligned silicide process is then conducted to form the salicide gates in both regions, and to selectively forming salicide layers on the source/drain regions in the logic region only.

Abstract: A method for forming a cylindrical capacitor of a dynamic random access memory cell is disclosed. The method includes firstly providing a semiconductor substrate having a dielectric layer thereon, at least one contact hole formed in the dielectric layer, wherein the contact hole extends from the top surface of the dielectric layer to the surface of the substrate. Next, a conductive layer is formed on the dielectric layer, and a blocking layer is further formed on the conductive layer. The conductive layer fills the contact hole, wherein at least one trench is formed in the blocking layer and a portion of the conductive layer, and wherein the trench locates approximately above the contact hole. Finally, an oxide layer is formed on the inner surface of the trench; and the blocking layer and a portion of the conductive layer are etched using the oxide layer as a mask, thereby forming a cylindrical electrode of the capacitor.

Abstract: A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.