Abstract: A top state controller controls a bus adapter to a selected master or slave top state in response to a command on a local or system bus during a dispatch state of the bus adapter. The bus adapter remains in the selected top state until the command is completed or suspended, whereupon it returns to the dispatch state. The top state controller sets a first flag upon a change from a master top state to the dispatch state in response to suspension of a command by a data handling device, and sets a second flag upon a change from a slave top state to the dispatch state upon completion of a command. The top state controller is responsive to the first or second flag to operate the bus adapter to that master top state from which the bus adapter changed to set the first flag and is responsive to the completion of the suspended command to clear the first and said second flags.

Abstract: A dual cache memory system employs a search cache addressed by virtual addresses, the search cache containing a plurality of recently used, pre-translated physical addresses. A map cache contains virtual address bound data and relocation data to map the virtual address space to physical address space. Upon receipt of a virtual address, a search of the search cache is first conducted to retrieve the associated physical address if it has been already translated. If not, a binary search of the memory map using the map cache is conducted to find that map entry whose virtual address bound identifies the region of virtual addresses containing the virtual address being mapped. The physical address is constructed from the retrieved relocation data and virtual address, and is written into the search cache for future use.

Abstract: A computer interface for interconnecting a plurality of computer modules in a multiplex manner to emulate a computer configuration includes transmitters and receivers associated with each master and slave module, together with logic means whereby the master module is permitted to initiate computer operations with acknowledgement from the slave to insure proper data speeds. Conflicts are resolved between master modules.