Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

Abstract: A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

Abstract: A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

Abstract: A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

Abstract: A PCIe (Peripheral Component Interconnect Express) protocol converter for connection to a central processing unit (CPU) node having a root complex, a CPU memory fabric and CPU memory may include independent PCIe links, a fabric interface and a fabric switch connected to the fabric interface. Each of the links may include an endpoint for connection to the root complex. The fabric switch is connected to the fabric interface of each of the links and is connectable to a remote node. The fabric switch transmits writes of a single write request from the remote node across both links. Each fabric interface is to transmit an acknowledgment to the remote node in response to a write of the writes becoming observable at the CPU node hi Michael, hi Michael,.

Abstract: A processing device includes a transceiver to be coupled to a link and control logic coupled to the transceiver. The control logic is to assign a unique sequence identifier to each packet to be transmitted across the link to a receiving node and transmit packets via the transceiver across the link to the receiving node. Each packet is to have a unique sequence identifier. The control logic also is to receive a message from the receiving node, the message containing the sequence identifier of a packet not correctly received by the receiving node. Based on the received message, the control logic is to cause an end-to-end negative acknowledgment (E2E NAK) packet to be transmitted to an originating node of the packet that was not correctly received.

Abstract: An example system for committing metadata to a non-volatile storage device may include a controller that includes determines a count of metadata that has been altered after being committed to the non-volatile storage device. Based on the count being above a first threshold, the controller may prevent alterations to the metadata. Based on the count being above a second threshold, the controller may commit the altered metadata to the non-volatile metadata.

Abstract: An example system for committing metadata to a non-volatile storage device may include a controller that includes determines a count of metadata that has been altered after being committed to the non-volatile storage device. Based on the count being above a first threshold, the controller may prevent alterations to the metadata. Based on the count being above a second threshold, the controller may commit the altered metadata to the non-volatile metadata.

Abstract: A processing device includes a transceiver to be coupled to a link and control logic coupled to the transceiver. The control logic is to assign a unique sequence identifier to each packet to be transmitted across the link to a receiving node and transmit packets via the transceiver across the link to the receiving node. Each packet is to have a unique sequence identifier. The control logic also is to receive a message from the receiving node, the message containing the sequence identifier of a packet not correctly received by the receiving node. Based on the received message, the control logic is to cause an end-to-end negative acknowledgment (E2E NAK) packet to be transmitted to an originating node of the packet that was not correctly received.

Abstract: The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Abstract: Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

Abstract: Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

Abstract: Systems, methodologies, media, and other embodiments associated with data recovery are described. One exemplary system embodiment includes a sampling logic configured to sample data from a data line using a timing reference that is selectable from a plurality of timing reference signals. The system may also include a symbol history logic configured to track a symbol history of the data sampled by the sampling logic and a timing selection logic configured to select the timing reference used to sample the data based on the symbol history of the data to compensate for inter-symbol interference.

Abstract: The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Abstract: A one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common storage system, and demultiplexer and control circuitry. The demultiplexer and control circuitry are configured so that cycle information destined for the first I/O bus interface is enqueued from the system bus interface into the first logical FIFO and is dequeued from the first logical FIFO into the first I/O bus interface. Cycle information destined for the second I/O bus interface is enqueued from the system bus interface into the second logical FIFO and is dequeued from the second logical FIFO into the second I/O bus interface. A level-of-fullness monitor monitors the common storage system and generates first and second level-of-fullness indications responsive thereto. The system bus interface is operable to declare I/O halt and I/O resume conditions on a system bus responsive to halt and resume commands.

Abstract: A multiple logical FIFO system uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. In a first embodiment, the free register identifier is implemented using a priority encoder. In a second embodiment, the free register identifier is implemented using a conventional FIFO buffer. In a third embodiment, the free register identifier is implemented using one of the logical FIFO buffers stored in the main register file.

Abstract: A bus bridge is disclosed that provides an interface between two computer buses and guarantees the proper ordering of write operations mastered from one bus relative to read operations mastered from the other bus where the presence of write posting storage in the bus bridge could cause ordering violations. The bus bridge includes a first mechanism for counting the number of write operations that are received by the bus bridge and queued in the write posting storage. In addition, the bus bridge includes a second mechanism for counting the number of write operations completed on the second bus. A mechanism for measuring the age of data held in each cache line of a coherent cache is also included as part of the bus bridge. Finally, the bus bridge includes a mechanism for delaying the completion of a read operation from the cache until all writes that were accepted by the bus bridge on the first bus before the cache data was fetched have been completed on the second bus.