Abstract: Apparatus and methods for time-delayed thermal overload protection are provided. In one aspect, an integrated circuit includes a primary circuit disposed in a primary circuit region on a substrate, and a thermal protection circuit disposed in a thermal protection circuit region on the substrate and in thermal communication with the primary circuit. The thermal protection circuit includes a temperature sensing circuit configured to sense a temperature of the thermal protection circuit region and to activate a temperature warning signal when the temperature exceeds a temperature threshold level. The thermal protection circuit additionally includes a time delay circuit configured to activate a shut off signal to disable at least a portion of the primary circuit when the temperature warning signal is active for a duration exceeding a time delay.

Abstract: Apparatus and methods are disclosed, such as those involving a junction field effect transistor for voltage protection. One such apparatus includes a protection circuit including an input, an output, and a JFET. The JFET has a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude. The apparatus further includes an internal circuit having an input configured to receive a signal from the output of the protection circuit. The protection circuit provides protection over the internal circuit from overvoltage and/or undervoltage conditions while having a reduced size compared to a JFET having a Vp of smaller than 2 V in magnitude.

Abstract: Apparatus and methods are disclosed, such as those involving a junction field effect transistor for voltage protection. One such apparatus includes a protection circuit including an input, an output, and a JFET. The JFET has a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude. The apparatus further includes an internal circuit having an input configured to receive a signal from the output of the protection circuit. The protection circuit provides protection over the internal circuit from overvoltage and/or undervoltage conditions while having a reduced size compared to a JFET having a Vp of smaller than 2 V in magnitude.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: A multiple op amp IC with a single low noise op amp configuration comprises at least two op amp circuits fabricated on a common substrate. The IC can be configured such that the multiple op amps are connected in parallel to form a single op amp having output drive and input-referred noise characteristics which are superior to those of the constituent op amps. The IC can be fabricated with either first or second metallization patterns, with the first pattern providing multiple op amps with separate inputs and outputs, and the second pattern interconnecting the amplifiers to form a single op amp. The second pattern also preferably interconnects at least one set of corresponding high impedance nodes to prevent a difference voltage which might otherwise arise between the nodes due to component mismatches between the multiple op amps.

Abstract: A multiplying current mirror provides at least one base current compensation stage between two other stages that establish a desired gain n. (n?1) compensation stages are provided for n>1, and [(1/n)?1] compensation stages for n<1. The compensation stages can be established as series connected repetitions of a basic cell stage. Each stage after the first includes a diode-connected bipolar transistor, with a low overall transistor count.

Abstract: A dynamically variable spectral matrix surround system decodes two-channel stereo into multi-channel surround. In one embodiment, the true stereo signal is present in left and right front and left and right surround channel outputs. When a dominant center channel signal appears, the system subtracts center channel audio from the critical voice band only. The higher frequency portion of the spectrum will remain true stereo at all times. In another embodiment, the front center signal bandwidth is determined. A dynamically variable portion of the audio spectrum is inverted and added to the opposite channel, thereby dynamically subtracting the bandwidth of the front center signal from the left front, left surround, right front and right surround channels but leaving the portion of the audio spectrum that does not contain front center information unaltered. The input is divided into two frequency bands.

Abstract: A high output current negative feedback power amplifier amplifies an input signal by use of a monolithic operated amplifier with a current limiting resistor in its output path. The output current of the amplifier is automatically increased when the voltage drop across the current limiting resistor increases beyond a predetermined point and global current limiting automatically occurs when the output current of the monolithic amplifier exceeds a predetermined point.

Abstract: A high output current negative feedback power amplifier amplifies an input signal by use of a monolithic operated amplifier with a current limiting resistor in its output path. The output current of the amplifier is automatically increased when the voltage drop across the current limiting resistor increases beyond a predetermined point and global current limiting automatically occurs when the output current of the monolithic amplifier exceeds a predetermined point.

Abstract: A voltage amplifier circuit inhibits excessive output phase shifts from a voltage amplifier that could result in oscillation, while still providing for rail-to-rail outputs. A first output stage that includes a blocking impedance dominates the output for low output values, while a second output stage that excludes the blocking impedance dominates for higher output voltages up to rail-to-rail. The output stages are preferably implemented with CMOS transistors, with the relative sizes of the transistors and the resistance of the blocking resistor selected to enable both phase shift inhibition and rail-to-rail outputs. The first output stage provides more AC feedback, while the second output stage provides more DC feedback for high output voltages.

Abstract: Unwanted voltage drops associated with the bit switches of a DAC are compensated with an output amplifier circuit for the DAC that includes a feedback circuit with a switch compensation resistance element that is connected in a combined series/parallel circuit with a feedback resistance circuit, so as to reduce both the size and associated capacitance of the resistance element.

Abstract: A low temperature coefficient (TC) voltage output circuit compensates for the TC of a base circuit's output voltage with a compensation circuit that includes first and second current sources with different TCs. The differential between the current sources is applied to a voltage drop circuit that generates a temperature dependent compensation voltage with a TC of opposite polarity to the TC of the base circuit's output. To provide compensation over a desired temperature range, the two current sources are set equal to each other at one temperature within the range, and the compensated voltage output is trimmed at another temperature within the range to the desired output value. The result is a compensated voltage, with a TC of opposite polarity to that of the base circuit's output, which combines with the base circuit output to yield a low TC compensated output. The compensation scheme is particularly useful for voltage references.

Abstract: A power-on reset circuit employs all-CMOS circuitry to initiate a reset signal when the circuit's power supply voltage is low, and terminate the signal in response to the supply voltage exceeding a reference voltage by at least the greater of the threshold voltages of PFET and NFET transistors employed in the circuit. A diode-connected bipolar transistor is implemented with an FET-compatible circuit structure to establish the reference voltage, which compensates for the possibility of fabrication tolerances.

Abstract: A power-on reset circuit employs all-CMOS circuitry to initiate a reset signal when the circuit's power supply voltage is low, and terminate the signal in response to the supply voltage exceeding a reference voltage by at least the greater of the threshold voltages of PFET and NFET transistors employed in the circuit. A diode-connected bipolar transistor is implemented with an FET-compatible circuit structure to establish the reference voltage, which compensates for the possibility of fabrication tolerances.

Abstract: A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

Abstract: A power-on reset circuit initiates a reset signal when the circuit's power supply voltage is low, and terminates the signal in response to the supply voltage exceeding a reset termination threshold that is based upon the greater of the threshold voltages for p-channel and n-channel FETs employed in the circuit. The reset termination threshold is preferably the sum of the greater FET threshold plus a safety margin, with the termination delayed by a predetermined period to ensure an adequate reset period, and a hysteresis feature added to ensure a stable reset termination.

Abstract: An ESD protection circuit allows a certain level of ESD current to flow through a protected circuit, and actuates a bypass path for greater ESD current levels when the sensed current reaches a threshold level. For a protected circuit having a pair of differential input terminals and a reference voltage terminal, the bypass path is provided between an input terminal which receives an ESD and the reference voltage terminal when the reference voltage is fixed, and between the two input terminals when the reference voltage is floating. The bypass circuit is preferably implemented with a pair of bipolar transistors of a first conductivity that are actuated by an ESD current flow through the protected circuit, and a pair of bipolar transistors of opposite conductivity that are actuated by current flows through the first conductivity transistors.

Abstract: A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

Abstract: Operational transconductance amplifiers (OTAs) are combined at their outputs, yielding a single frequency compensation connection point. In a preferred embodiment, the output of each OTA is asymmetric, i.e., they can only source current and the OTA outputs are tied together to a constant current sink. Consequently, the OTA that sources more current controls the voltage of the merged output. This merged output point provides a voltage output that may be used as a frequency compensation point.