Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

Abstract: A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

Abstract: A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The output buffer includes a pullup transistor and a pulldown transistor for applying an output signal to an I/O pad. When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Also, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor.

Abstract: A Boundary-Scan register (BSR) cell including a bypass circuit for selectively routing data signals around the data shift register of the BSR cell so that the BSR cell can be effectively removed from a BSR chain during Boundary-Scan Test procedures involving IEEE Standard 1149.1 compliant integrated circuits. In one embodiment, the BSR cell includes a bypass MUX having a first input terminal connected to a test data input (TDI) terminal of the BSR cell, a second input terminal connected to an output terminal of the shift register, and an output terminal connected to the test data output (TDO) terminal. The BSR cell operates in a “normal” mode (i.e., included in the BSR chain) when the bypass MUX is controlled to pass data signals output from the shift register to the TDO terminal. In contrast, the BSR cell is selectively bypassed (i.e., removed from the BSR chain) when the bypass MUX is controlled to pass the TDI signal to the TDO terminal.

Abstract: A negative voltage detector is disclosed wherein a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider of the present invention allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

Abstract: A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed.

Abstract: An input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal of an integrated circuit device, such as a Programmable Logic Device (PLD). The I/O circuit includes pull-up and pull-down transistors for generating output signals on the I/O terminal in an output mode, and an isolation transistor for limiting the voltage level transmitted to the pull-up transistor from the I/O terminal in an input mode. The isolation transistor is formed with a thicker gate oxide and a longer channel length than that of the pull-up and pull-down transistors, thereby allowing the isolation transistor to withstand voltages greater than Vcc of the PLD without damage. The isolation transistor is controlled using a charge pump provided on the PLD for programming non-volatile memory cells (e.g., EPROM, EEPROM or flash EPROM cells). The isolation transistor is produced during the same process steps used to produce high voltage transistors associated with the non-volatile memory cells.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage.

Abstract: A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

Abstract: The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.

Abstract: A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.