Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs translation lookaside buffer coherency for a translation lookaside buffer of the graphics processing unit of the device. In this embodiment, the device receives a request to remove an entry of the translation lookaside buffer of the graphics processing unit, where the device includes a central processing unit and the graphics processing unit. In addition, the entry includes a translation of virtual memory address of a process to a physical memory address of system memory of a central processing unit and the graphics processing unit is executing a compute task of the process. The device locates the entry in the translation lookaside buffer and removes the entry.

Abstract: A method and apparatus of a device that coalesces the execution of several timers by scheduling the timers using a scheduling window is described. The device determines a scheduling window for each of several timers. The device selects a coalesced execution time that is within the scheduling window of the timers. The device coalesces the execution of the timers by scheduling the timers to execute at the coalesced execution time. The device can further coalesce multiple timers by opportunistic execution of the timers. In response to a detection of an opportunistic execution trigger event, the device receives multiple timers. The device selects a subset of the timers to execute based on an initial execution time and a latency time for each of the timers. The device schedules each of the subset of timers to execute during or before the opportunistic execution trigger event.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling graphics processing unit operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilizes a graphics processing unit of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first GPU utilization for the low priority process and maintains a second GPU utilization for the high priority process. The device further executes the low priority process using the first GPU utilization with the GPU and executes the high priority process using the second GPU utilization with the GPU.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling input/output operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilize storage of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first bandwidth range for the low priority process and maintains a second bandwidth range for the high priority process. The device further processes a storage request of the low priority process using the first bandwidth range and processing a storage request of the high priority process using the second bandwidth range.

Abstract: A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling input/output operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilize storage of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first bandwidth range for the low priority process and maintains a second bandwidth range for the high priority process. The device further processes a storage request of the low priority process using the first bandwidth range and processing a storage request of the high priority process using the second bandwidth range.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling graphics processing unit operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilizes a graphics processing unit of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first GPU utilization for the low priority process and maintains a second GPU utilization for the high priority process. The device further executes the low priority process using the first GPU utilization with the GPU and executes the high priority process using the second GPU utilization with the GPU.

Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device monitors the thermal profile of the device, where the device executes a plurality of tasks that utilizes a central processing unit of the device. In addition, the plurality of tasks includes a high QoS task and a low QoS process. If the thermal profile of the device exceeds a thermal threshold, the device increases a first CPU throttling for the low QoS task and maintains a second CPU throttling for the high QoS task. The device further executes the low QoS task using the first CPU utilization with the first processing core of the CPU by selectively forcing an idle of the low QoS task during an execution window. In addition, the device executes the high QoS task using the second CPU throttling with a second processing core of the CPU.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs translation lookaside buffer coherency for a translation lookaside buffer of the graphics processing unit of the device. In this embodiment, the device receives a request to remove an entry of the translation lookaside buffer of the graphics processing unit, where the device includes a central processing unit and the graphics processing unit. In addition, the entry includes a translation of virtual memory address of a process to a physical memory address of system memory of a central processing unit and the graphics processing unit is executing a compute task of the process. The device locates the entry in the translation lookaside buffer and removes the entry.

Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.

Abstract: A method and apparatus of a device that coalesces the execution of several timers by scheduling the timers using a scheduling window is described. The device determines a scheduling window for each of several timers. The device selects a coalesced execution time that is within the scheduling window of the timers. The device coalesces the execution of the timers by scheduling the timers to execute at the coalesced execution time. The device can further coalesce multiple timers by opportunistic execution of the timers. In response to a detection of an opportunistic execution trigger event, the device receives multiple timers. The device selects a subset of the timers to execute based on an initial execution time and a latency time for each of the timers. The device schedules each of the subset of timers to execute during or before the opportunistic execution trigger event.

Abstract: A method and apparatus of a device that rate-limits the execution of a timer is described. The device receives a timer that includes an initial execution timer and a timer priority. If the timer priority is low, the device rate-limits the execution of the timer based on a suppression period associated with the timer priority. In order to rate-limit the execution of the timer, the device determines the suppression period based on the timer priority and schedules the timer to execute at the end of the suppression period. The device further schedules the timer to execute at the initial exertion time when the timer priority is high.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.