Abstract: A method of planarizing a semiconductor wafer to a distance from a semiconductor substrate of the wafer is disclosed. The method includes the step of forming in the wafer a metallic reporting substance that is at the predetermined distance from the substrate of the wafer. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. The method further includes the step of utilizing an atomic absorption spectroscopic technique to detect the presence of the metallic reporting substance in the material removed from the wafer. Moreover, the method includes the step of terminating the polishing step in response to the detection of the metallic reporting substance. An associated apparatus for polishing a semiconductor wafer down to a metallic reporting substance of the wafer is also described.

Abstract: The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor.

Abstract: A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

Abstract: The present invention applies a silicon nitride or the like as a mask over portions of a substrate, such as an active region, where oxide growth is undesired. Thereafter, without the formation of a recess in the substrate, a high pressure oxidation process is used to grow an oxide, preferably in a furnace. The oxide thus grows into the non-masked areas of the substrate, as well as over the silicon nitride used as a mask. Thereafter, a chemical-mechanical polish is used to etch away undesired oxide, with the silicon nitride being used as an endpoint to terminate the polish operation.

Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.

Abstract: The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Abstract: A polishing composition is shown which includes (1) a polishing media particle; (2) a film forming binder for suspending the particle and forming a temporary film on an exposed surface of the workpiece, the temporary film being dissolvable in a subsequently applied polishing wash, whereby the polishing media particle is freed to polish the workpiece; (3) a solvent for suspending the polishing media particle in the film forming binder to facilitate forming the temporary film; and (4) a wetting agent to improve the wettability of the composition on the exposed surface of the workpiece.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

Abstract: There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.

Abstract: A method is shown for polishing a workpiece such as a semiconductor wafer. A polishing composition is first formed which includes (1) a polishing media particle; and (2) a film forming binder for suspending the particle and forming a temporary film on an exposed surface of the workpiece, the temporary film being dissolvable in a subsequently applied polishing wash, whereby the polishing media particle is freed to polish the workpiece. The polishing composition is applied to the surface of the semiconductor wafer in a spin coating operation and thereafter cured in a hot plate bake or a furnace operation. In order to polish the workpiece, a polishing wash is applied to either or both of the surface of the workpiece or a polishing pad and thereafter causing the pad to be sufficiently proximate to the surface of the workpiece at a pressure and for a time sufficient to polish and planarize the workpiece.

Abstract: A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

Abstract: There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.

Abstract: There is disclosed doped spin-on glass compositions such as boronoxide doped spin-on glass compositions with a high carbon content and silane adhesion promoter incorporated therein for use as coating layers on substrates such as silicon wafers.

Abstract: A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A shallow junction spin on glass (SOG) process which provides shallow junction semiconductor devices without defects and leaky junctions. The process includes spinning first and second SOG layers containing first and second dopants onto a semiconductor substrate and diffusing the dopants into the substrate to form first and second junctions. The diffusion time and temperature are controlled so as to produce junctions having depths less than a predetermined maximum depth. Insulating and metal interconnect layers are deposited on top of the SOG layers. The insulating layer may include boron-phosphorus silicon glass (BPSG).

Abstract: A method for forming a bipolar transistor which employs a single drive-in step to form an emitter and a base. A layer of SOG containing a plurality of dopants is spun onto a collector, typically silicon. The dopants are driven into the collector to form the base and emitter. The method employs diffusion instead of implanting to form shallow and abrupt junctions without damage to the crystal lattice of the silicon.

Abstract: A method for forming a bipolar emitter using doped SOG which employs diffusion instead of implanting, and which produces a shallow, low-resistance emitter using a variety of dopants besides boron and phosphorus. A layer of doped SOG is spun over a predefined base region. Portions of the SOG layer are defined for removal and removed, leaving the collector and emitter contact areas exposed. The SOG layer is densified and the dopants are driven into the base to form the emitter.

Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.