Abstract: In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.

Abstract: In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.