Patents by Inventor Dev A. Girdhar

Dev A. Girdhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8148815
    Abstract: An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: April 3, 2012
    Assignee: Intersil Americas, Inc.
    Inventors: Dev A. Girdhar, Thomas A. Jochum, Bogdan M. Duduman
  • Publication number: 20100090668
    Abstract: An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.
    Type: Application
    Filed: April 16, 2009
    Publication date: April 15, 2010
    Inventors: Dev A. Girdhar, Thomas A. Jochum, Bogdan M. Duduman
  • Publication number: 20060060916
    Abstract: A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 23, 2006
    Inventors: Dev Girdhar, Ling Ma