Patents by Inventor Devadatta V. Bodas

Devadatta V. Bodas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11435809
    Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
  • Publication number: 20210365096
    Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.
    Type: Application
    Filed: May 3, 2021
    Publication date: November 25, 2021
    Applicant: Intel Corporation
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
  • Patent number: 10996737
    Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
  • Patent number: 10719107
    Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada
  • Patent number: 10404676
    Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: September 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Andy Hoffman, Mariusz Oriol, Gopal R. Mundada
  • Patent number: 10345884
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don C. Soltis, Jr., Hang T. Nguyen, Cyprian W. Woo, Thi Dang
  • Patent number: 10037069
    Abstract: Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: INTEL CORPORATION
    Inventors: Neven M. Abou Gazala, James W. Alexander, Devadatta V. Bodas
  • Patent number: 9939834
    Abstract: A system and method for computing at a facility having systems of multiple compute nodes to execute jobs of computing. Power consumption of the facility is managed to within a power band. The power consumption may be adjusted by implementing (e.g., by a power balloon) activities having little or no computational output.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman, Michael K. Patterson
  • Patent number: 9857858
    Abstract: A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, John H. Crawford, Alan G. Gara
  • Publication number: 20170285702
    Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Brian J. Griffith, Andy Hoffman, Gopal R. Mundada
  • Publication number: 20170285717
    Abstract: A system with improved power performance for task executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: DEVADATTA V. BODAS, MURALIDHAR RAJAPPA, JUSTIN J. SONG, ANDY HOFFMAN
  • Publication number: 20170289300
    Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Andy Hoffman, Mariusz Oriol, Gopal Mundada
  • Publication number: 20170115716
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Application
    Filed: August 16, 2016
    Publication date: April 27, 2017
    Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, MARTIN T. ROWLAND, CHRIS POIRIER, ERIC J. DEHAEMER, AVINASH N. ANANTHAKRISHNAN, JEREMY J. SHRALL, XIUTING C. MAN, STEPHEN H. GUNTHER, KRISHNA K. RANGAN, DEVADATTA V. BODAS, DON SOLTIS, HANG T. NGUYEN, CYPRIAN W. WOO, THI DANG
  • Patent number: 9588823
    Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 7, 2017
    Assignee: Intel Corporation
    Inventors: Muralidhar Rajappa, Andy Hoffman, Devadatta V. Bodas, Justin J. Song, James W. Alexander
  • Publication number: 20170003730
    Abstract: Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 7, 2016
    Publication date: January 5, 2017
    Inventors: Neven M. Abou Gazala, James W. Alexander, Devadatta V. Bodas
  • Patent number: 9524009
    Abstract: A method and system for managing the operation of a computing system are described herein. The method includes determining a number of workloads on the computing system. The method also includes determining a number of performance-power states for each workload and a corresponding performance range and power consumption range for each performance-power state. The method further includes managing performance and power consumption of the computing system based on the performance-power states.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, John H. Crawford
  • Patent number: 9417681
    Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan, Jeremy J. Shrall, Xiuting C. Man, Stephen H. Gunther, Krishna K. Rangan, Devadatta V. Bodas, Don Soltis, Hang T. Nguyen, Cyprian W. Woo, Thi Dang
  • Publication number: 20160187906
    Abstract: A system and method for computing at a facility having systems of multiple compute nodes to execute jobs of computing. Power consumption of the facility is managed to within a power band. The power consumption may be adjusted by implementing (e.g., by a power balloon) activities having little or no computational output.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: INTEL CORPORATION
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman, Michael K. Patterson
  • Publication number: 20160187395
    Abstract: A system and method for forecasting power consumption at a facility, the facility having a system of compute units for executing jobs of computing. The forecast of power includes forecasting sequence of jobs execution on a system of the nodes over time, estimating power for the jobs of the system, and developing a system-level power forecast.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: INTEL CORPORATION
    Inventors: Devadatta V. Bodas, Muralidhar Rajappa, Justin J. Song, Andy Hoffman
  • Publication number: 20160188379
    Abstract: A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job executing on the compute nodes are adjusted to increase performance of the job or to lower power consumption of the job, or both, wherein the adjusting is based on imbalances of respective speeds of the parallel tasks.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: Muralidhar Rajappa, Andy Hoffman, Devadatta V. Bodas, Justin J. Song, James W. Alexander