Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a buffer amplifier circuit, having an input coupled to Q1 and an output coupled to Q2. The offset of the buffer amplifier circuit can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror, while being able to reduce the buffer offset due to mismatch between master and slave sides of the current mirror circuit.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a buffer amplifier circuit, having an input coupled to Q1 and an output coupled to Q2. The offset of the buffer amplifier circuit can be adjusted by including circuitry for an input or an output side offset adjustment or by implementing the buffer amplifier circuit as a diamond stage with individually controlled current sources for each of the transistors of the diamond stage. Providing an adjustable offset buffer in a current mirror arrangement may advantageously allow benefiting from the use of a buffer outside of a feedback loop of a current mirror, while being able to reduce the buffer offset due to mismatch between master and slave sides of the current mirror circuit.

Abstract: An example current mirror arrangement includes a current mirror circuit having an input transistor and an output transistor, where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors. Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.

Abstract: An example current mirror arrangement includes a first portion and a second portion, each of which includes a current mirror having transistors Q1 and Q2, a buffer amplifier that has an input coupled to a base/gate terminal of Q1 and an output coupled to a base/gate terminal of Q2, a master resistor coupled to an emitter/source terminal of Q1, and a slave resistor coupled to an emitter/source terminal of Q2. Furthermore, the slave resistor of the first portion is coupled to the slave resistor of the second portion. Providing additional resistors on master and slave sides of a current mirror arrangement may advantageously allow benefiting from the use of buffers outside of a feedback loop of a current mirror while reducing the sensitivity of the current mirror arrangement to buffer offsets.

Abstract: A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (IIN) and generate a mirrored current (IM), where IM=K*IIN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1?m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.

Abstract: Embodiments of the present disclosure provide an optical range finder that includes a transimpedance amplifier (TIA) and a photodiode emulation circuitry for testing the TIA. The photodiode emulation circuitry may be coupled to an input port of the TIA and configured to receive one or more parameters specifying one or more characteristics of a test current signal to be provided to the TIA. The photodiode emulation circuitry may further be configured to provide the test current signal in accordance with the one or more parameters to the input port of the TIA while the photodiode is also coupled to the input port of the TIA.

Abstract: Embodiments of the present disclosure provide an optical range finder that includes a transimpedance amplifier (TIA) and a photodiode emulation circuitry for testing the TIA. The photodiode emulation circuitry may be coupled to an input port of the TIA and configured to receive one or more parameters specifying one or more characteristics of a test current signal to be provided to the TIA. The photodiode emulation circuitry may further be configured to provide the test current signal in accordance with the one or more parameters to the input port of the TIA while the photodiode is also coupled to the input port of the TIA.

Abstract: In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

Abstract: In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

Abstract: The bootstrapped switch for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor having a first end coupled to a control node of the bootstrapped switch, and having a backgate coupled to a second end of the first transistor; a first capacitor having a first end coupled to a second end of the first transistor; a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the second end of the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter having a first output coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; a fifth transistor having a first end coupled to a control node of the fourth transis

Abstract: The bootstrapping circuit capable of sampling inputs beyond supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor having a first end coupled to a control node of the bootstrapped switch, and having a backgate coupled to the second end of the first transistor; a first capacitor having a first end coupled to a second end of the first transistor; a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the second end of the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter having an output coupled to a second end of the first capacitor; a fourth transistor cross coupled with the first transistor, and having a backgate coupled to the second end of the fourth transistor; a fifth transistor having a second end coupled to the first end of

Abstract: An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.

Abstract: The bootstrapping circuit capable of sampling inputs beyond supply voltage includes: a bootstrapped switch MN20 coupled between an input node and an output node; a first transistor MP13 having a first end coupled to a control node of the bootstrapped switch MN20; a clock bootstrapped capacitor C13 having a first end coupled to a second end of the first transistor MP13; a second transistor MN27 coupled between the first end of the first transistor MP13 and a supply node, and having a control node coupled to a first clock signal node PHI; a third transistor MN26 coupled between the second end of the first transistor MP13 and the supply node; a charge pump having a first output coupled to a control node of the third transistor MN26; a level shifter having a first output coupled to a second end of the clock bootstrapped capacitor C13; a fourth transistor MN25 coupled between the supply node and a control node of the first transistor MP13, and having a control node coupled to a second output of the charge pump; a