Abstract: Bus error injection circuit generates bus errors to test proper operation of bus error detection and recovery in a system of modules interconnected by a synchronous digital bus. Application of the circuit is bus error detection and recovery tests for a physical realization of the system. The bus error injection circuit can be replicated on a number of modules interconnected by a synchronous bus to provide multiple sources of error injection. One module, or multiple modules, with error injection circuitry is designated as the source(s) to inject a transient bus error. The bus error injection circuitry monitors the bus to determine when the module is a participant in a bus transfer cycle on the bus. An error injection counter decrements for each such cycle. When the counter output value is one, the module derives its error injection pattern onto bus signal lines in place of the signal line values normally generated.