Abstract: Disclosed are methods, systems and non-transitory computer readable memory for gesture inference. For instance, a first method may include computer vision to train and/or infer gesture inferences. For instance, a second method may include using transformations to data and/or ML models to address inter/intra-session variability of sensor data. For instance, a third method may include using ML model selection to select a ML model to address inter/intra-session variability of sensor data.

Abstract: Disclosed are methods, systems and non-transitory computer readable memory for gesture inference. For instance, a first method may include computer vision to train and/or infer gesture inferences. For instance, a second method may include using transformations to data and/or ML models to address inter/intra-session variability of sensor data. For instance, a third method may include using ML model selection to select a ML model to address inter/intra-session variability of sensor data.

Abstract: Provided are integrated locks, aircraft galley systems using such locks, and aircraft including such galley systems. An integrated lock has a low profile and provides secure locking and visual indication of the lock status to meet various FAA regulations. The visual indication may be provided mechanically (e.g., by moving a two-color indicator between two positions) or electronically (e.g., by triggering a switch connected to a light or an electro-chromic device). Furthermore, a main indicator may be connected to multiple different locks to provide a combined visual indication of the status of all locks. A visual indicator may be disposed on a galley system frame. Each integrated lock may include a handle portion and a locking portion connected to the handle portion and configured to engage the galley system frame when the handle portion is in the locked position and the door is closed.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

Abstract: Provided are integrated locks, aircraft galley systems using such locks, and aircraft including such galley systems. An integrated lock has a low profile and provides secure locking and visual indication of the lock status to meet various FAA regulations. The visual indication may be provided mechanically (e.g., by moving a two-color indicator between two positions) or electronically (e.g., by triggering a switch connected to a light or an electro-chromic device). Furthermore, a main indicator may be connected to multiple different locks to provide a combined visual indication of the status of all locks. A visual indicator may be disposed on a galley system frame. Each integrated lock may include a handle portion and a locking portion connected to the handle portion and configured to engage the galley system frame when the handle portion is in the locked position and the door is closed.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: Provided are integrated locks, aircraft galley systems using such locks, and aircraft including such galley systems. An integrated lock has a low profile and provides secure locking and visual indication of the lock status to meet various FAA regulations. The visual indication may be provided mechanically (e.g., by moving a two-color indicator between two positions) or electronically (e.g., by triggering a switch connected to a light or an electro-chromic device). Furthermore, a main indicator may be connected to multiple different locks to provide a combined visual indication of the status of all locks. A visual indicator may be disposed on a galley system frame. Each integrated lock may include a handle portion and a locking portion connected to the handle portion and configured to engage the galley system frame when the handle portion is in the locked position and the door is closed.

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

Abstract: Provided are integrated locks, aircraft galley systems using such locks, and aircraft including such galley systems. An integrated lock has a low profile and provides secure locking and visual indication of the lock status to meet various FAA regulations. The visual indication may be provided mechanically (e.g., by moving a two-color indicator between two positions) or electronically (e.g., by triggering a switch connected to a light or an electro-chromic device). Furthermore, a main indicator may be connected to multiple different locks to provide a combined visual indication of the status of all locks. A visual indicator may be disposed on a galley system frame. Each integrated lock may include a handle portion and a locking portion connected to the handle portion and configured to engage the galley system frame when the handle portion is in the locked position and the door is closed.

Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Abstract: A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.

Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Abstract: A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.