Abstract: A circuit, a method and a system for automatic level switching are provided. The circuit for automatic level switching comprises a level selector, a chip IO interface and a level detector; wherein, each input terminal of the level selector is connected to a different input voltage, and an output terminal of the level selector provides the chip IO interface with an interface level; the chip IO interface is connected to an off-chip device; a control terminal of the level detector is connected to a control terminal of the level selector, and a detection terminal of the level detector is connected to the chip IO interface.

Abstract: A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Abstract: A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Abstract: A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

Abstract: A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.

Abstract: A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.

Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.

Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.

Abstract: A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.

Abstract: A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.

Abstract: An electric skateboard is disclosed. In one aspect, the electric skateboard comprises a foot placement section. The electric skateboard comprises a wheel suspension truck connected to the foot placement section. The electric skateboard comprises a first wheel and a second wheel, wherein the first wheel and the second wheel are spaced apart and substantially parallel to one another and wherein the first wheel and the second wheel are connected to the wheel suspension truck. The electric skateboard comprises a deformation sensor module attached to the wheel suspension truck, the deformation sensor module configured to generate a weight signal and a gravity angle signal associated with the electric skateboard. The electric skateboard comprises a control logic configured to output control signals that control a movement of the electric skateboard in response to the weight signals, and the gravity angle signals.

Abstract: Various embodiments of fractional-N phase-locked loop (PLL) frequency synthesizers based on digital-to-analog conversion (DAC) are disclosed. In some embodiments, a PLL frequency synthesizer includes a phase-frequency detector, a voltage controlled oscillator (VCO) coupled to the phase-frequency detector, and a digital-to-analog converter (DAC) coupled between an input of the phase-frequency detector and an output of the VCO within a feedback path of the PLL frequency synthesizer. The phase-frequency detector is configured to receive a reference input clock and an output signal of the DAC as a feedback input clock. Furthermore, the DAC receives an output clock from the VCO and a digital control signal comprising frequency and phase information for synthesizing the feedback input clock. The disclosed DAC-based PLL frequency synthesizers do not require any frequency divider in a feedback path of the PLL, thereby significantly reducing power consumption and noise levels.

Abstract: A two-wheel, self-balancing vehicle comprises a first wheel and a second wheel, spaced apart and substantially parallel to one another; a foot placement section connecting the first wheel and the second wheel; a set of position sensors in the foot placement section, the set of position sensors configured to generate inclination angle signals and velocity signals of the two-wheel, self-balancing vehicle; a first gravity sensor and a second gravity sensor in the foot placement section, the first gravity sensor and the second gravity sensor configured to generate weight signals and gravity angle signals. In addition, the two-wheel, self-balancing vehicle comprises a control logic configured to output control signals that control the movement of the two-wheel, self-balancing vehicle in response to the inclination angle signals, the velocity signals, the weight signals, and the gravity angle signals.

Abstract: A two-wheel, self-balancing vehicle is disclosed. In one aspect, the two-wheel, self-balancing vehicle comprises a first wheel and a second wheel, the first wheel and the second wheel being spaced apart and substantially parallel to one another. The two-wheel, self-balancing vehicle further comprises a foot placement section connecting the first wheel and the second wheel. The two-wheel, self-balancing vehicle further comprises a set of position sensors in the foot placement section, the set of position sensors configured to generate inclination angle signals and velocity signals of the two-wheel, self-balancing vehicle. The two-wheel, self-balancing vehicle further comprises a first gravity sensor and a second gravity sensor in the foot placement section, the first gravity sensor and the second gravity sensor configured to generate weight signals and gravity angle signals.