Abstract: This application provides a charging plug and socket-outlet, charging and to-be-charged apparatuses, a charging system, and a control method. The charging system includes: a charging apparatus and a to-be-charged apparatus. The charging apparatus includes a charging plug and a first cooling system. The charging plug includes a first electrical transmission interface, a first heat conduction output interface, and a first heat conduction input interface. The to-be-charged apparatus includes a battery, a charging socket-outlet, and a second cooling system. The charging socket-outlet includes a second electrical transmission interface, a second heat conduction output interface, and a second heat conduction input interface. The solutions of this application can be used to meet a heat dissipation requirement of the battery in the to-be-charged apparatus during super charging.

Abstract: A conductive mounting structure for a lighting lamp. The lighting lamp comprises a first assembly (1) connected to a power supply and a second assembly (2) having a light source; the first assembly (1) comprises a first mounting member (11), and the second assembly (2) comprises a second mounting member (21). The first assembly (1) and the second assembly (2) are connected by using a connection structure. The connection structure comprises a contact (3), and a conductive component (4) conducted after being in contact with the contact (3), the contact (3) and the conductive component (4) are respectively provided on the first mounting member (11) and the second mounting member (21), and the contact (3) is in contact with the conductive component (4) after the first assembly (1) and the second assembly (2) are assembled and combined.

Abstract: A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.

Abstract: A method for diagnosing a diesel oxidation catalyst fault includes: obtaining an standard molar enthalpy of formation-revolution speed-load table; obtaining a revolution speed, a load, a temperature difference of front and rear exhaust pipes, and a casing temperature, obtaining an standard molar enthalpy of formation corresponding to the revolution speed and the load from the standard molar enthalpy of formation-revolution speed-load table, and calculating an actual formation enthalpy corresponding to the temperature difference of front and rear exhaust pipes and the casing temperature from the temperature difference of front and rear exhaust pipes and the casing temperature; calculating a standard reaction enthalpy from the standard molar enthalpy of formation and standard conversion efficiency; and diagnosing a diesel oxidation catalyst fault by comparing the actual formation enthalpy with the standard reaction enthalpy.

Abstract: An input device and an input method are provided. An example input device may include a projection module configured to project an image. The projection module is configured to be movable to cause a variation in the projected image. The variation indicates direction information about the movement to control movement of a controlled target.

Abstract: The invention provides a cache device and method for performing a cache process on a cache memory having a high capacity in a high speed. The cache processing section performs a cache process composed of two-stage processes, a query process (P1) and a subsequent process (P2). In the query process (P1), the respective index tables and the identifier table are used to query whether the target identifier is present in the cache memory at a step (S101). If it is present, a data address of the target identifier in the cache memory is transmitted to the CPU. Otherwise, a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step (S102). In a subsequent process (P2), adjustment operations for the respective tables, regarding insertion of an identifier for a new data and deletion of the identifier for the ultimate LRU data, are performed at a step (S201).

Abstract: The invention provides a cache device and method for performing a cache process on a cache memory having a high capacity in a high speed. The cache processing section performs a cache process composed of two-stage processes, a query process (P1) and a subsequent process (P2). In the query process (P1), the respective index tables and the identifier table are used to query whether the target identifier is present in the cache memory at a step (S101). If it is present, a data address of the target identifier in the cache memory is transmitted to the CPU. Otherwise, a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step (S102). In a subsequent process (P2), adjustment operations for the respective tables, regarding insertion of an identifier for a new data and deletion of the identifier for the ultimate LRU data, are performed at a step (S201).