Abstract: A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.

Abstract: The trench depth is optimized in such a way that the locations for electron and hole injections into the storage layer (11), which is disposed in boundary layers (10, 12) between the trench walls and the gate electrode (4), coincide. The junctions (14) at which the doping of the source zone (2) and the drain zone (3) changes into the opposite sign (i.e. that of the conductivity type of the semiconductor body (1)) and which border the channel region (5) abut a curved region of the trench bottom (7) or a curved lower region of the lateral trench walls (6, 8).

Abstract: An integrated circuit in complementary circuit technology comprises a substrate bias voltage generator which reverse biases the substrate, into which tubs of opposite conductivity are inserted. The source regions of the field effect transistors arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, the output of the substrate bias voltage generator is connected by way of an electronic switch to a circuit point lying at ground potential, whereby the switch is driven via the output of the substrate bias voltage generator.

Abstract: An integrated circuit executed in complementary circuit technology, has a substrate bias generator (16) which connects the substrate (1) to a substrate bias. A well (2) of opposite conductivity is inserted into the substrate (1), and FETs with complementary channels are inserted into the substrate (1) and into the well (2), respectively. The source regions (3) of the FET's of first conductivity lie at ground potential. In order to avoid latch-up effects, the output (17) of the substrate bias generator (16) is connected via an electronic switch (S1) to a circuit point (8) lying at ground potential, the switch being driven via a time-delay circuit (24) charged with the supply voltage so that it opens with a prescribed time-delay after the supply voltage is applied.

Abstract: An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.

Abstract: A method for manufacturing MNOS memory transistors with very short channel lengths in silicon gate technology. In a substrate of a first semiconductor type, source and drain zones of MNOS and MOS components of a second conductivity type opposite the first conductivity type are provided. The edges of gate electrodes, with reference to the plane of the substrate surface, lie perpendicularly and self-adjusting over the edges of the source and drain zones, whereby the source and drain zones generated in the substrate are manufactured by means of ion implantation upon employment of the gate electrodes as the implantation mask.