Patents by Inventor Dharaneedharan SHANMUGASUNDARAM

Dharaneedharan SHANMUGASUNDARAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Noise immune data path scheme for multi-bank memory architecture
    Patent number: 10140224
    Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mukund Narasimhan, Sharad Kumar Gupta, Dharaneedharan Shanmugasundaram
  • NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE
    Publication number: 20180113821
    Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.
    Type: Application
    Filed: March 16, 2017
    Publication date: April 26, 2018
    Inventors: Mukund NARASIMHAN, Sharad Kumar GUPTA, Dharaneedharan SHANMUGASUNDARAM