Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.

Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.

Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.

Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.

Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.

Abstract: A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal.

Abstract: A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal.