Abstract: Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

Abstract: Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

Abstract: Systems and methods relate to extending life of a low-dropout (LDO) voltage regulator. A differential amplifier of the LDO voltage regulator includes switches that can be selectively turned on or off. When the LDO voltage regulator is bypassed or turned off (or not active), a first switch is turned on to selectively couple gates of a first input transistor and a second input transistor of the differential amplifier, to maintain the gates at a same voltage. The first switch is turned off to decouple the gates when the LDO voltage regulator is active. Further, a second switch can be turned on or off to selectively couple or decouple, respectively, the gate of the second input transistor to an output voltage of the LDO voltage regulator, based on whether the LDO voltage regulator is active or not active, respectively.

Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.

Abstract: Aspects of generating asynchronous clock signals for successive approximation register (SAR) analog to digital converters (ADCs) are disclosed. In one aspect, an asynchronous clock generator circuit is provided that is configured to receive a voltage generated by a comparator in a SAR ADC, and generate an outside-window signal in response to the voltage being outside of a voltage threshold window. The asynchronous clock generator circuit is configured to generate a trigger signal in response to the outside-window signal coinciding with the asynchronous clock signal being in an inactive state. In response to the trigger signal being in an active state for a minimum time, the asynchronous clock generator circuit is configured to generate an edge signal, and generate the asynchronous clock signal having a pulse width in response to the edge signal. The asynchronous clock generator circuit adaptively generates the asynchronous clock signal according to timing of each comparison.

Abstract: Switched power control circuits for controlling the rate of providing voltages to powered circuits are disclosed. In one aspect, a switched power control circuit is provided that is configured to control activation of a headswitch circuit such that the headswitch circuit gradually provides a supply voltage to a powered circuit rather than providing full supply voltage in a substantially instantaneous manner. To gradually ramp up an output voltage, the headswitch circuit is configured to provide the output voltage to the powered circuit in response to a control signal received on a control input. The control signal is generated by a control circuit in response to an enable signal. To prevent the headswitch circuit from providing the full supply voltage to the powered circuit instantaneously, a current sink circuit is configured to control a ramping rate of the output voltage generated by the headswitch circuit.

Abstract: Switched power control circuits for controlling the rate of providing voltages to powered circuits are disclosed. In one aspect, a switched power control circuit is provided that is configured to control activation of a headswitch circuit such that the headswitch circuit gradually provides a supply voltage to a powered circuit rather than providing full supply voltage in a substantially instantaneous manner. To gradually ramp up an output voltage, the headswitch circuit is configured to provide the output voltage to the powered circuit in response to a control signal received on a control input. The control signal is generated by a control circuit in response to an enable signal. To prevent the headswitch circuit from providing the full supply voltage to the powered circuit instantaneously, a current sink circuit is configured to control a ramping rate of the output voltage generated by the headswitch circuit.

Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.

Abstract: Systems and methods relate to extending life of a low-dropout (LDO) voltage regulator. A differential amplifier of the LDO voltage regulator includes switches that can be selectively turned on or off. When the LDO voltage regulator is bypassed or turned off (or not active), a first switch is turned on to selectively couple gates of a first input transistor and a second input transistor of the differential amplifier, to maintain the gates at a same voltage. The first switch is turned off to decouple the gates when the LDO voltage regulator is active. Further, a second switch can be turned on or off to selectively couple or decouple, respectively, the gate of the second input transistor to an output voltage of the LDO voltage regulator, based on whether the LDO voltage regulator is active or not active, respectively.

Abstract: Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.

Abstract: Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase.

Abstract: Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.

Abstract: Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.

Abstract: Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.