Abstract: A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).

Abstract: A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Abstract: A digital-to-analog converter (20) with improved performance includes an offset/scaler (23), a sigma-delta modulator (25), and an analog summing network (26). In one embodiment, the offset/scaler (23) scales an input signal by a predetermined amount, such as three-quarters, to compensate for nonlinearities in a transfer characteristic of the sigma-delta modulator (25). In another embodiment, the sigma-delta modulator (25) is a sufficiently-resolved sigma-delta modulator. The offset/scaler (23) provides an offset to the sufficiently-resolved sigma-delta modulator (25) sufficient to force a coarse bit thereof into an idle pattern.