Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

Abstract: Techniques for managing page tables for an accelerated processing device are provided. The page tables for the accelerated processing device include a primary page table and secondary page tables. The page size selected for any particular secondary page table is dependent on characteristics of the memory allocations for which translations are stored in the secondary page table. Any particular memory allocation is associated with a particular “initial” page size. Translations for multiple allocations may be placed into a single secondary page table, and a particular page size is chosen for all such translations. The page size is the smallest of the natural page sizes for the allocations that are not using a translate further technique. The translation further technique is a technique wherein secondary page table entries do not themselves provide translations but instead point to an additional page table level referred to as the translate further page table level.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: Techniques for managing page tables for an accelerated processing device are provided. The page tables for the accelerated processing device include a primary page table and secondary page tables. The page size selected for any particular secondary page table is dependent on characteristics of the memory allocations for which translations are stored in the secondary page table. Any particular memory allocation is associated with a particular “initial” page size. Translations for multiple allocations may be placed into a single secondary page table, and a particular page size is chosen for all such translations. The page size is the smallest of the natural page sizes for the allocations that are not using a translate further technique. The translation further technique is a technique wherein secondary page table entries do not themselves provide translations but instead point to an additional page table level referred to as the translate further page table level.

Abstract: Systems, apparatuses, and methods for implementing a translate further mechanism are disclosed herein. In one embodiment, a processor detects a hit to a first entry of a page table structure during a first lookup to the page table structure. The processor retrieves a page table entry address from the first entry and uses this address to perform a second lookup to the page table structure responsive to detecting a first indication in the first entry. The processor retrieves a physical address from the first entry and uses the physical address to access the memory subsystem responsive to not detecting the first indication in the first entry. In one embodiment, the first indication is a translate further bit being set. In another embodiment, the first indication is a page directory entry as page table entry field not being activated.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.