Patents by Inventor Dian Yang

Dian Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Design verification by symbolic simulation using a native hardware description language
    Publication number: 20040015800
    Abstract: A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 22, 2004
    Inventors: John Xiaoxiong Zhong, Dian Yang, Zheng Zhou, Ting Wang
  • Design verification by symbolic simulation using a native hardware description language
    Patent number: 6634012
    Abstract: A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: October 14, 2003
    Assignee: Innologic Systems, Inc.
    Inventors: John Xiaoxiong Zhong, Dian Yang, Zheng Zhou, Ting Wang
  • DESIGN VERIFICATION BY SYMBOLIC SIMULATION USING A NATIVE HARDWARE DESCRIPTION LANGUAGE
    Publication number: 20030066039
    Abstract: A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
    Type: Application
    Filed: September 14, 1999
    Publication date: April 3, 2003
    Inventors: JOHN XIAOZIONG ZHONG, DIAN YANG, ZHENG ZHOU, TING WANG
  • Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system
    Patent number: 5469366
    Abstract: A technique is described which is generally directed to providing better delay determination for "nets" (equivalent circuits of point-to-point wiring) in integrated circuit designs on a semiconductor design automation system by adapting general RC-mesh networks representing those "nets" to efficient nodal matrix circuit solver techniques which are not inherently suited to general RC-mesh circuits. This is accomplished by "collapsing" the general RC-mesh network into an RC-tree equivalent circuit (network) which can be solved (simulated) by such nodal matrix techniques, thus determining node voltages and waveforms for each of the nodes of the simplified network. After solving the simplified network, the simplified network is re-expanded into its original RC-mesh form, determining the node voltages and waveforms at the re-expanded nodes thereof (eliminated during the collapse of the network) by applying simple circuit analysis techniques.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: November 21, 1995
    Assignee: LSI Logic Corporation
    Inventors: Dian Yang, Hashain Karampurwala