Abstract: According to some embodiments of the present invention, an avalanche photodiode includes a first electrode, a second electrode spaced apart from the first electrode, a photon absorber layer formed to be in electrical connection with the first electrode, and a charge-carrier multiplication layer formed to be in electrical connection with the second electrode. The photon absorber layer is a semiconducting material that has a first lattice constant, and the charge-carrier multiplication layer is a semiconducting material that has a second lattice constant that is different from the first lattice constant. The photon absorber layer and the charge-carrier multiplication layer are connected together by an interfacial misfit (IMF) array at an interface thereof such that the IMF array provides at least part of an acceleration potential for an avalanche region of the avalanche photodiode.

Abstract: An optoelectronic device includes: (1) a top transparent electrode; (2) a bottom electrode spaced apart from the top transparent electrode; and (3) nanopillars arranged between the top transparent electrode and the bottom electrode such that each of the nanopillars includes a top end electrically connected to the top transparent electrode and a bottom end electrically connected to the bottom electrode. The top transparent electrode is shaped to provide optical elements each arranged to couple light into or out of a respective one of the nanopillars.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: Embodiments provide a quantum dot active structure and a methodology for its fabrication. The quantum dot active structure includes a substrate, a plurality of alternating regions of a quantum dot active region and a strain-compensation region, and a cap layer. The strain-compensation region is formed to eliminate the compressive strain of an adjacent quantum dot active region, thus allowing quantum dot active regions to be densely-stacked. The densely-stacked quantum dot active region provides increased optical modal gain for semiconductor light emitting devices such as edge emitting lasers, vertical cavity lasers, detectors, micro-cavity emitters, optical amplifiers or modulators.

Abstract: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.

Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.

Abstract: A method for removing a mask in a selective area epitaxy process is provided. The method includes forming a first layer on a substrate and oxidizing the first layer. A patterned photoresist can be formed on the oxidized first layer. A portion of the oxidized first layer can then be removed using a wet chemical etch to form a mask. After removing the patterned photoresist a second layer can be epitaxially grown in a metal organic chemical vapor deposition (MOCVD) chamber or a chemical beam epitaxy (CBE) chamber on a portion of the first layer exposed by the mask. The mask can then be removed the mask in the MOCVD/MBE chamber. The disclosed in-situ mask removal method minimizes both the atmospheric exposure of a growth surface and the number of sample transfers.

Abstract: Disclosed is a low threshold vertical cavity surface emitter having a low refraction index confining layer directly in the cavity spacer. This allows a ½ wavelength cavity spacer and a lateral size of as low as 2 &mgr;m. Also disclosed is a method of rapid temperature annealing to seal a III-V crystal and inhibit oxidative degradation.

Abstract: Disclosed is a low threshold vertical cavity surface emitter having a low refraction index confining layer (36) directly in the cavity spacer. This allows a ½ wavelength cavity spacer and lateral size of as low as 2 &mgr;m. Also disclosed is a method of rapid temperature annealing to seal a III-V crystal and inhibit oxidative degradation.