Patents by Inventor Diane Catherine Boyd

Diane Catherine Boyd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly
    Patent number: 6440808
    Abstract: A sub-0.1 &mgr;m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Diane Catherine Boyd, Stephen Bruce Brodsky, Hussein Ibrahim Hanafi, Ronnen Andrew Roy
  • Mosfet with high dielectric constant gate insulator and minimum overlap capacitance
    Publication number: 20020028555
    Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
    Type: Application
    Filed: May 25, 2001
    Publication date: March 7, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane Catherine Boyd, Hussein Ibrahim Hanafi, Meikei Ieong, Wesley Charles Natzle
  • MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
    Patent number: 6353249
    Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: March 5, 2002
    Assignee: International Businsess Machines Corporation
    Inventors: Diane Catherine Boyd, Hussein Ibrahim Hanafi, Meikei Ieong, Wesley Charles Natzle
  • Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
    Patent number: 6271094
    Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: August 7, 2001
    Assignee: International Business Machines Corporation
    Inventors: Diane Catherine Boyd, Hussein Ibrahim Hanafi, Meikei Ieong, Wesley Charles Natzle
  • Disposable-spacer damascene-gate process for SUB 0.05 &mgr;m MOS devices
    Patent number: 6245619
    Abstract: Techniques to fabricate sub−0.05 &mgr;m MOSFET devices with Super-Halo doping profile which provide excellent short-channel characteristics are provided. The techniques utilize a damascene-gate process to obtain MOSFET structures with oxide thickness above the source/drain region independent of the gate-oxide thickness and a disposable-spacer technique for the formation of the Super-Halo doping profile.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: June 12, 2001
    Assignee: International Business Machines Corporation
    Inventors: Diane Catherine Boyd, Hussein Ibrahim Hanafi, Wesley Charles Natzle