Abstract: A low power dissipation circuit for generating clock pulses comprises a plurality of solid state devices which are normally off and draw only leakage current in their quiescent state. The clock pulse is started by a signal to a set side driver and is stopped by a signal to a reset side driver. The input drivers remain on only during the time they are being driven. The output drivers for generating the clock pulse comprises a pair of switching transistors which remain on only while the clock switching pulses are being generated.

Abstract: A compatible standby power driving circuit for a dynamic semiconductor memory includes a low impedance, high power driving circuit connected in parallel with a high impedance, low power driving circuit. The outputs of the high power and low power driving circuits are mutually connected to the column driving circuit output and the inputs of both driving circuits are connected to the refresh address selection line so that both the output of the high power driving circuit and the low power driving circuit are available under normal or regular power conditions and the low power driving circuit output is available under standby power conditions.