Patents by Inventor Didier Farenc

Didier Farenc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200036218
    Abstract: An apparatus is disclosed for wireless power transfer circuitry with a multi-path architecture. In an example aspect, the apparatus includes a wireless power receiver with at least one receiving element, at least one output power node, and two or more power paths having at least one power path configured to be selectively activated. The two or more power paths are coupled between the at least one receiving element and the at least one output power node.
    Type: Application
    Filed: March 19, 2019
    Publication date: January 30, 2020
    Inventors: Joseph Maalouf, Sumukh Ashok Shevde, Didier Farenc, Cheong Kun, Georgios Konstantinos Paparrizos
  • Publication number: 20190372466
    Abstract: Aspects of the disclosure are directed to direct battery connection within a voltage regulator system. In accordance with one aspect, distributing power from an internal battery as an active energy source includes receiving a battery voltage from the internal battery through a direct battery voltage connection; receiving a primary load voltage from a power conditioner; and regulating and combining the battery voltage and the primary load voltage using a plurality of phased regulator sections to generate a common output voltage. In one aspect, a power distribution system includes an internal battery to function as an active energy source for a load; a battery switch coupled to the internal battery; a power management integrated circuit (PMIC) coupled to the battery switch; and a direct battery voltage connection coupling the internal battery to the power management integrated circuit and bypassing the battery switch.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Inventor: Didier FARENC
  • Publication number: 20040031996
    Abstract: A semiconductor device (10) having asymmetric source and drain regions is formed so that either the source or drain region is shorted to an isolated well (22). In one embodiment, the source region includes a source silicide region (42) and a source extension region (28), which are electrically and physically in contact with the well region (22), and the drain region includes a drain silicide region (46), a drain extension region (30) and a deep doped drain region (38). The source and drain regions have a conductivity that is different than that of the isolated well (22) in which they are formed. To prevent the formation of a deep doped source region when the deep doped drain region (38) is formed, a masking layer (34) is patterned to cover the source region during implantation of the deep doped drain region (38).
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Inventors: Chi Nan Brian Li, Didier Farenc, Kuo-Tung Chang