Abstract: The invention relates to using persistent luminescence nanoparticles, functionalised if necessary, in the form of an diagnosis agent for an in vivo optical imaging. Said nanoparticles are preferably consist of a compound selected from a group comprising (1) silicates, aluminates, aluminosilicates, germanates, titanates, oxysulphides, phosphates and vanadates, wherein said compounds contain at least one type of metal oxide, (2) the sulphides comprise at least one metal ion selected from zinc, strontium and calcium, and (3) metal oxides, wherein said compounds is doped with at least one rare earth ion, and possibly with at least one transition metal ion. In a preferred embodiment, the diagnosis agent is used for an organism vascularization imaging. A method and kit for detecting or quantifying in vitro a substance of biological or chemical interest in a sample by using said pre-functionalised nanoparticles are also disclosed.

Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.

Abstract: Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.

Abstract: A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer and capable of connecting to at least one conductive area of a microelectronic device. The interconnection structure has an improved low dielectric constant. The interconnection structures may be a metal interconnection structure in a variety of integrated circuits.

Abstract: This invention relates to a process for manufacturing interconnection structures, including: a) the formation on a substrate of a first layer comprising one or several conducting zones (24) and one or several insulating zones made of an organic material (26), b) coverage of this first layer by a porous layer (28), c) consumption and elimination of at least part of the organic material through the porous layer, using enzymes and/or proteins.

Abstract: Facing surfaces made from semiconductor material are formed and then transformed into a porous semiconductor. The porous semiconductor is then transformed into a porous metallic material by silicidation. The porous metallic material then acts as catalyst for growth of the carbon nanotubes which electrically connect the facing surfaces made from porous metallic material.

Abstract: The invention relates to using persistent luminescence nanoparticles, functionalised if necessary, in the form of an diagnosis agent for an in vivo optical imaging. Said nanoparticles are preferably consist of a compound selected from a group comprising (1) silicates, aluminates, aluminosilicates, germanates, titanates, oxysulphides, phosphates and vanadates, wherein said compounds contain at least one type of metal oxide, (2) the sulphides comprise at least one metal ion selected from zinc, strontium and calcium, and (3) metal oxides, wherein said compounds is doped with at least one rare earth ion, and possibly with at least one transition metal ion. In a preferred embodiment, the diagnosis agent is used for an organism vascularisation imaging. A method and kit for detecting or quantifying in vitro a substance of biological or chemical interest in a sample by using said pre-functionalised nanoparticles are also disclosed.

Abstract: This invention relates to a process for manufacturing interconnection structures, including: a) the formation on a substrate of a first layer comprising one or several conducting zones (24) and one or several insulating zones made of an organic material (26), b) coverage of this first layer by a porous layer (28), c) consumption and elimination of at least part of the organic material through the porous layer, using enzymes and/or proteins.

Abstract: A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer and capable of connecting to at least one conductive area of a microelectronic device. The interconnection structure has an improved low dielectric constant. The interconnection structures may be a metal interconnection structure in a variety of integrated circuits.

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up.

Abstract: A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the components of a first and second input vectors into the ANN; engaging all the neurons of a same prototype; having all the neurons compute their own distance between the respective prototypes and the second input vector (which should be the same if the neurons were good); determining the minimum distance Dmin and comparing Dmin with a distance D measured between the first and the second input vectors. If Dmin<D, it is indicative that at least one failing neuron exists (i.e., either the distance, the category or the AIF value differs from a predetermined expected value), in which case the failing neuron is isolated.

Abstract: The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the feed back and control signals. The R/W memory block, typically a RAM, is common to all neurons to avoid circuit duplication, increasing thereby the number of neurons integrated in the chip. The R/W memory stores the prototype components. Each neuron comprises a computation block, a register block, an evaluation block and a daisy chain block to chain the neurons. All these blocks (except the computation block) have a symmetric structure and are designed so that each neuron may operate in a dual manner, i.e. either as a single neuron (single mode) or as two independent neurons (dual mode). Each neuron generates local signals.

Abstract: The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other.

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up.

Abstract: In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS).

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector.

Abstract: An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.<1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to "zero" and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS).

Abstract: A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0.In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the "carry out" output. The "Force Carry" input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.