Abstract: A network interface device includes a fabric interface, adapted to exchange messages over a switch fabric with a plurality of host processors, the messages containing data, and a network interface, including one or more ports adapted to be coupled to a network external to the switch fabric. Message processing circuitry is coupled between the fabric interface and the network interface, so as to enable at least first and second host processors among the plurality of the host processors to use a single one of the ports substantially simultaneously so as to transmit and receive frames containing the data over the network.

Abstract: A method for static rate flow control includes receiving a sequence of data packets for transmission over a network, including at least first and second packets having a common destination address on the network, the first and second packets having respective first and second lengths, and transmitting the first packet to the destination address. Responsive to transmitting the first packet, an entry is placed in a flow control table, and a timeout period is set for the entry responsive to the first length. The second packet is transmitted only after the timeout period has expired.

Abstract: A method for communication between a network interface adapter and a host processor coupled thereto includes writing information using the network interface adapter to a location in a memory accessible to the host processor. Responsive to having written the information, the network interface adapter places an event indication in an event queue accessible to the host processor. It then asserts an interrupt of the host processor that is associated with the event queue, so as to cause the host processor to read the event indication and, responsive thereto, to process the information written to the location.

Abstract: A network interface adapter includes a network interface, coupled to send and receive data packets over a network and a host interface, for coupling to a host processor and to a system memory associated therewith. The system memory contains context information with respect to a plurality of transport service instances used to send and receive the data packets over the network, each of the data packets belonging to a respective one of the service instances. Packet processing circuitry, coupled between the network interface and the host interface, processes the data packets using the context information of the respective service instances. A cache memory associated with the packet processing circuitry is coupled to load from the system memory and store the context information of the respective transport service instances for the data packets being processed by the packet processing circuitry.

Abstract: A network interface adapter provides a host processor with two complementary modes of submitting descriptors to be executed by the adapter: a normal mode, in which the host writes descriptors to a system memory and rings an assigned doorbell to notify the adapter; and a priority mode, in which the host writes the descriptor itself to a doorbell address of the adapter. In the priority mode, the adapter is relieved of the need to read the descriptor from the memory, and can thus begin execution as soon as it has resources available to do so.

Abstract: A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface adapter that couples the host device to the network and allocating instances of a communication service on the network, to be provided via the adapter, to the processes. Upon receiving a request submitted by a given one of the processes to its respective doorbell address to access one of the allocated service instances, the adapter conveys the data over the network using the specified instance of the service, subject to verifying, based on the doorbell address to which the request was submitted, that the specified instance was allocated to the given process.

Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.

Abstract: A method for communication over a network includes receiving from a host processor a descriptor defining a message including message data to be sent over the network, and responsive to the descriptor, generating a sequence of packets each containing a respective portion of the message data. An indication is entered in a selected packet among the packets in the sequence, other than the final packet, requesting that a recipient of the packets acknowledge the selected packet. Following an interruption in the sequence of the packets subsequent to the selected packet, sending of the packets in the sequence resumes beginning after the selected packet.

Abstract: A network interface adapter includes an outgoing packet generator, adapted to generate an outgoing request packet for delivery to a remote responder responsive to a request submitted by a host processor and a network output port, coupled to transmit the outgoing request packet over a network to the remote responder. A network input port receives an incoming response packet from the remote responder, in response to the outgoing request packet sent thereto, as well as an incoming request packet sent by a remote requester. An incoming packet processor receives and processes both the incoming response packet and the incoming request packet, and causes the outgoing packet generator, responsive to the incoming request packet, to generate, in addition to the outgoing request packet, an outgoing response packet for transmission to the remote requester.

Abstract: An interface adapter for a packet network includes a first plurality of execution engines, coupled to a host interface so as to read from a memory work items corresponding to messages to be sent over the network, and to generate gather entries defining packets to be transmitted over the network responsive to the work items. A scheduling processor assigns the work items to the execution engines for generation of the gather entries. Switching circuitry couples the execution engines to a plurality of gather engines, which generate the packets responsive to the gather entries.

Abstract: A device for switching packets in a network includes a switching core and a plurality of ports, coupled to pass the packets from one to another through the switching core. The ports include, with respect to each packet among the packets switched by the device, a receiving port, coupled to receive the packet from a packet source, and a destination port, to which the packet is passed for conveyance to a packet destination. The ports also include one or more cache memories, respectively associated with one or more of the ports, each of the cache memories being configured to hold a forwarding database cache for reference by the receiving port with which the cache memory is associated in determining the destination port of the packet.

Abstract: A method of direct memory access (DMA) includes receiving a first notification at a DMA engine that a first list of descriptors has been prepared, each of the descriptors in the list including an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link. The DMA engine reads and executes the descriptors in the first list. When the DMA engine receives a second notification that a second list of the descriptors has been prepared, it rereads at least a part of the final descriptor in the first list to determine a changed value of the link, indicating a first descriptor in the second list. It then reads and executes the descriptors in the second list responsive to the changed value of the link.

Abstract: A method for link-level flow control includes establishing a plurality of logical links over a physical link between a transmitting entity and a receiving entity in a network. Respective maximum limits of transmission credits are assigned to the logical links, the credits corresponding to space available to the links in a dynamically allocable portion of a receive buffer at the receiving entity, such that a sum of the maximum limits for all of the logical links corresponds to an amount of space substantially larger than a total volume of the space in the dynamically allocable portion of the receive buffer.

Abstract: A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.