Abstract: A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented.

Abstract: A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented.

Abstract: According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant.

Abstract: According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: The acid copper sulfate solutions used for electroplating copper circuitry in trenches and vias in IC dielectric material in the Damascene process are replaced with a type of plating system based on the use of highly complexing anions (e.g., pyrophosphate, cyanide, sulfamate, etc.) to provide an inherently high overvoltage that effectively suppresses runaway copper deposition. Such systems, requiring only one easily-controlled organic additive species to provide outstanding leveling, are more efficacous for bottom-up filling of Damascene trenches and vias than acid copper sulfate baths, which require a minimum of two organic additive species. The highly complexed baths produce fine-grained copper deposits that are typically much harder than large-grained acid sulfate copper deposits, and which exhibit stable mechanical properties that do not change with time, thereby minimizing “dishing” and giving more consistent CMP results.

Abstract: An improved microelectronic device and methods for forming the device are disclosed. The device includes a conductive feature formed on a semiconductor wafer by creating a trench within an insulating material, depositing barrier material substantially only within the trench, depositing conductive material on the wafer surface and within the trench, and removing the conductive material from the wafer surface. Alternately, the barrier material may be deposited onto the wafer surface and the trench and removed from the wafer surface prior to conductive material deposition.

Abstract: A method for the removal and purification of substantially all of the fluoride ions contained in a solution containing greater than 10 parts per million (ppm) fluoride ion, a mixture of other anions, silicon in the form of a fluorosilicic acid, silicic acid, silicates, or silicon tetrafluoride, and optionally also containing complex metal fluorides, to produce an ultrapure hydrofluoric acid, comprising the steps of (a) adjusting the pH of the solution to an alkaline pH to hydrolyze the fluorosilicic acid and any complex metal fluorides; (b) removing the fluoride ions and other anions from the solution by passing the solution through an ion exchange resin, where the ion exchange resin is adapted to adsorb substantially all of the fluoride passed over the ion exchange resin; (c) displacing the fluoride ions and other anions bound to the ion exchange resin, thereby forming a mixture of anions in an effluent emanating from resin; (d) optionally concentrating the effluent at a high pH and then lowering the pH; and