Patents by Inventor Dietrich Bonart
Dietrich Bonart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160204075Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.Type: ApplicationFiled: January 13, 2016Publication date: July 14, 2016Inventors: Dietrich BONART, Ludger BORUCKI, Martina DEBIE, Bernhard WEIDGANS
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Publication number: 20160155677Abstract: Various embodiments provide a semiconductor device, wherein the semiconductor device comprises a semiconductor device chip formed at a substrate, wherein the semiconductor device chip comprises an active region formed in a center of the substrate and a boundary region free of active components of the semiconductor device chip; and a detection wiring arranged in the boundary region of the substrate and at least partially surrounding the active region, wherein the detection wiring and the semiconductor device chip are electrically isolated from each other; and wherein the detection wiring and the substrate are electrically connected with each other via a connection having a high electrical resistance.Type: ApplicationFiled: November 28, 2015Publication date: June 2, 2016Inventors: Dietrich BONART, Alfred Goerlach
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Patent number: 9324625Abstract: A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a semiconductor die and the drain zone directly adjoins an opposite second surface of the semiconductor die. The drain zone includes a drift zone formed in an epitaxial layer of the semiconductor die. Base zones of a second conductivity type, which is the opposite of the first conductivity type, are provided between the drain zones and the source zones. The drift zone further includes adjustment zones directly adjoining a base zone and arranged between the respective base zone and the second surface, respectively. A net dopant concentration in the adjustment zone is at least twice a net dopant concentration in the second sub-zone. The adjustment zones precisely define the reverse breakdown voltage.Type: GrantFiled: May 31, 2012Date of Patent: April 26, 2016Assignee: Infineon Technologies AGInventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
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Patent number: 9318485Abstract: In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped regions, wherein the first doped regions are doped with dopants of a first conductivity type and the second doped regions are doped with dopants of a second conductivity type being opposite to the first conductivity type, and wherein the plurality of first doped regions and the plurality of second doped regions are alternatingly arranged next to each other in the substrate; a dielectric layer disposed over the plurality of first doped regions and the plurality of second doped regions; an electrode disposed over the dielectric layer; a first terminal electrically coupled to each doped region of the plurality of first doped regions and the plurality of second doped regions; and a second terminal electrically coupled to the electrode.Type: GrantFiled: August 10, 2012Date of Patent: April 19, 2016Assignee: INFINEON TECHNOLOGIES AGInventor: Dietrich Bonart
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Patent number: 9293371Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: GrantFiled: June 24, 2015Date of Patent: March 22, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Publication number: 20160064362Abstract: An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate.Type: ApplicationFiled: September 5, 2014Publication date: March 3, 2016Inventor: Dietrich Bonart
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Patent number: 9275895Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.Type: GrantFiled: January 28, 2014Date of Patent: March 1, 2016Assignee: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20150294911Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: ApplicationFiled: June 24, 2015Publication date: October 15, 2015Inventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Patent number: 9093385Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: GrantFiled: May 28, 2013Date of Patent: July 28, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Publication number: 20140357055Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.Type: ApplicationFiled: May 28, 2013Publication date: December 4, 2014Applicant: Infineon Technologies AGInventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
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Patent number: 8846452Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.Type: GrantFiled: August 21, 2012Date of Patent: September 30, 2014Assignee: Infineon Technologies AGInventor: Dietrich Bonart
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Publication number: 20140227147Abstract: A microfluidic device includes a semiconductor chip having a main chip surface. The microfluidic device further includes an encapsulation body embedding the semiconductor chip, the encapsulation body having a main body surface. A microfluidic component extends over the main chip surface and over the main encapsulation body surface and traverses an outline of the main chip surface.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Stefan Beyer, Dietrich Bonart
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Publication number: 20140141608Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20140057393Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: INFINEON TECHNOLOGIES AGInventor: Dietrich Bonart
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Publication number: 20140042591Abstract: In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped regions, wherein the first doped regions are doped with dopants of a first conductivity type and the second doped regions are doped with dopants of a second conductivity type being opposite to the first conductivity type, and wherein the plurality of first doped regions and the plurality of second doped regions are alternatingly arranged next to each other in the substrate; a dielectric layer disposed over the plurality of first doped regions and the plurality of second doped regions; an electrode disposed over the dielectric layer; a first terminal electrically coupled to each doped region of the plurality of first doped regions and the plurality of second doped regions; and a second terminal electrically coupled to the electrode.Type: ApplicationFiled: August 10, 2012Publication date: February 13, 2014Applicant: INFINEON TECHNOLOGIES AGInventor: Dietrich Bonart
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Patent number: 8637378Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: GrantFiled: June 9, 2011Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20130320915Abstract: A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a semiconductor die and the drain zone directly adjoins an opposite second surface of the semiconductor die. The drain zone includes a drift zone formed in an epitaxial layer of the semiconductor die. Base zones of a second conductivity type, which is the opposite of the first conductivity type, are provided between the drain zones and the source zones. The drift zone further includes adjustment zones directly adjoining a base zone and arranged between the respective base zone and the second surface, respectively. A net dopant concentration in the adjustment zone is at least twice a net dopant concentration in the second sub-zone. The adjustment zones precisely define the reverse breakdown voltage.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Dirk Ahlers, Markus Zundel, Dietrich Bonart, Ludger Borucki
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Publication number: 20130240882Abstract: A die in accordance with various embodiments may include a metallization area located proximate an edge of the die, and an electrical connection connected to the metallization area and running from the metallization area to the edge, wherein the electrical connection is free from metal. A wafer in accordance with various embodiments may include a die region having a metallization area, a kerf region having an electric or electronic device, and an electrical connection connecting the electric or electronic device with the metallization area, wherein the electrical connection is free from metal.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Dietrich Bonart
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Patent number: 8476734Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: GrantFiled: June 9, 2011Date of Patent: July 2, 2013Assignee: Infineon Technologies AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross
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Publication number: 20110256688Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.Type: ApplicationFiled: June 9, 2011Publication date: October 20, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Andreas Meiser, Walter Hartner, Hermann Gruber, Dietrich Bonart, Thomas Gross