Abstract: In a method for manufacturing a field effect transistor, a semiconductor layer sequence is grown that has a channel layer (2), a barrier layer (3) and a highly doped InGaAs layer (6) suitable for low-impedance contacting to a metal contact. A passivation layer (8) of dielectric is applied and is structured for the region lying between source, gate and drain. An auxiliary layer (10) is applied by vapor-deposition in a very flat incident angle such that the gate region remains free. The semiconductor layers are etched out in the region of the gate down onto the barrier in a plurality of RIE etching processes. The auxiliary layer is removed, spacers are produced at the sidewalls of the passivation layer, a refractory metallization is deposited surface-wide and etched back in planarizing fashion, so that separate contacts for source, gate and drain derive. Finally, the terminal metallization is applied.

Abstract: A method for manufacturing a field effect transistor which includes one more spacer provided in the gate recess adjacent the drain sidewall than adjacent the source sidewall in the contact such that a gate metallization is displaced asymmetrically toward a source side sidewall of the recess; and method for manufacturing same wherein oblique vapor deposition of an auxiliary layer into a recess for the gate region makes it possible for a spacer therein at the source side to be removed whereas a spacer of the drain side remains in place, such that the subsequent gate metallization is positioned closer to the source than to the drain.

Abstract: A MESFET is disclosed wherein a gallium arsenide semiconductor material is doped. The doping magnitude differs in the source area, drain area, and in the gate area. An increase of the dielectric strength without an increase of parasitic resistances is provided. In the manufacture of the MESFET, shadowing techniques are employed to vary the doping magnitudes.

Abstract: Very thin semiconductor chips are produced from a relatively large semiconductor substrate (such as gallium arsenide substrate) by generating a select pattern of crystallographic stress areas in a front surface of the substrate, as by mechanical scoring or application of a layer of material having a coefficient of thermal expansion significantly different from that of the semiconductor material in a pattern corresponding to the desired chip; applying an etch-resistant carrier member to such stressed front surface and etching the entire back surface of the substrate into a thickness less than 50 .mu.m, whereby the etching reaction penetrates into the region of the crystallographic stress and a division of the resultant eroded body into individual chips corresponding to the selected patterns occurs, with the chips being carried by said carrier member.

Abstract: A MESFET is disclosed wherein a gallium arsenide semiconductor material is doped. The doping magnitude differs in the source area, drain area, and in the gate area. An increase of the dielectric strength without an increase of parasitic resistances is provided. In the manufacture of the MESFET, shadowing techniques are employed to vary the doping magnitudes.

Abstract: A planar Schottky diode is disclosed which is inserted into a transmission line without disruption of characteristic impedance. The diode comprises a plurality of parallel finger-like projections forming Schottky contacts distributed over a width of the transmission line and also of ohmic contacts surrounding these projections but with a longer contact edge.