Abstract: A data-processing system includes an address bus and a data bus operatively coupled to a central processing unit, main memories, and control circuits for peripheral equipment, information carried on the data bus being encrypted. An encryption and decryption device is operatively coupled between the data bus and the central processing unit, for encrypting and decrypting the information.

Abstract: A quadrature receiver is disclosed which contains two mixers (M1, M3) in an in-phase receiving path and two mixers (M2, M4) in a quadrature receiving path for converting a received signal to a low IF. Each of the mixers is fed with an oscillator signal (O1 through O4), with the oscillator signal fed to one mixer of the respective receiving path having alternately the same or opposite phase from that of the oscillator signal fed to the other mixer of the same receiving path. In each receiving path, the mixers are followed by a circuit (P', P") which delivers an in-phase signal and a quadrature signal, respectively. These circuits compensate for the DC offset caused by the mixers.

Abstract: A system for encrypted information transmission is disclosed in which so-called recording interference is suppressed. Encryption is effected by means of a periodically recurring pseudo-noise sequence (key word). Synchronization between transmitter and receiver is produced by means of a sync word. During the period of validity of the key word, each sync word is used only once. At least the sync words already used or the information derived therefrom are stored in a sync-word memory (SP). If a sync word appears twice, this indicates recording interference, and the associated information is suppressed.

Abstract: A working on the zero IF principle is disclosed which contains a feedback circuit instead of a preselector for suppressing interfering signals. The interfering signals contained in the incoming signal (F.sub.E) are separated from the useful signal by filters in the baseband. They are then reconverted to the RF value, amplified, and substracted from the incoming signal (F.sub.E) by a subtracter (S1). In the steady state, the output of the subtracter (S1) provides the useful signal, which is converted into the baseband and then fed to a signal processor (SV).