Patents by Inventor Digvijay Ashokkumar Raorane

Digvijay Ashokkumar Raorane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978948
    Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Digvijay Ashokkumar Raorane
  • Patent number: 11594493
    Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventor: Digvijay Ashokkumar Raorane
  • Publication number: 20210391638
    Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: Vijay K. Nair, Digvijay Ashokkumar Raorane
  • Patent number: 11195806
    Abstract: An integrated circuit (IC) comprises a substrate, a first die mounted on the substrate, a second die mounted on the substrate and a waveguide structure mounted on the first die and the second die to enable high frequency wireless communication between the first die and the second die.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Digvijay Ashokkumar Raorane
  • Publication number: 20210375719
    Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventors: Feras Eid, Shrenik Kothari, Chandra M. Jha, Johanna M. Swan, Michael J. Baker, Shawna M. Liff, Thomas L. Sounart, Betsegaw K. Gebrehiwot, Shankar Devasenathipathy, Taylor Gaines, Digvijay Ashokkumar Raorane
  • Publication number: 20210028117
    Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.
    Type: Application
    Filed: July 6, 2020
    Publication date: January 28, 2021
    Inventor: Digvijay Ashokkumar Raorane
  • Patent number: 10804117
    Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Digvijay Ashokkumar Raorane, Ravindranath V. Mahajan
  • Patent number: 10707169
    Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventor: Digvijay Ashokkumar Raorane
  • Publication number: 20200211966
    Abstract: Ceramic interposers in a disaggregated-die semiconductor package allow for useful signal integrity and interconnecting components. Low-loss ceramics are used to tune ceramic interposers for a die assembly that may have components from different process-technology nodes.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventor: Digvijay Ashokkumar Raorane
  • Publication number: 20200021007
    Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 16, 2020
    Inventors: Vijay K. Nair, Digvijay Ashokkumar Raorane
  • Publication number: 20190304809
    Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Digvijay Ashokkumar Raorane, Ravindranath V. Mahajan
  • Publication number: 20190267336
    Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include a substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed on the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 29, 2019
    Inventors: Digvijay Ashokkumar Raorane, Vijay K. Nair
  • Publication number: 20190267337
    Abstract: An integrated circuit (IC) comprises a substrate, a first die mounted on the substrate, a second die mounted on the substrate and a waveguide structure mounted on the first die and the second die to enable high frequency wireless communication between the first die and the second die.
    Type: Application
    Filed: December 29, 2016
    Publication date: August 29, 2019
    Inventors: Vijay K. NAIR, Digvijay Ashokkumar RAORANE
  • Publication number: 20190214328
    Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Feras Eid, Shrenik Kothari, Chandra M. Jha, Johanna M. Swan, Michael J. Baker, Shawna M. Liff, Thomas L. Sounart, Betsegaw K. Gebrehiwot, Shankar Devasenathipathy, Taylor Gaines, Digvijay Ashokkumar Raorane