Abstract: A method of operation for a Reed-Solomon decoder includes receiving partial input data of symbols of a Reed-Solomon codeword; updating Reed-Solomon syndromes and error location polynomial coefficients based on the partial input data; maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding; and inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of Reed-Solomon decoding including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection based on the first error evaluator polynomial to determine presence and location of errors in an input Reed-Solomon codeword, and updating the error location polynomial when errors are found in the input Reed-Solomon codeword.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.

Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.