Patents by Inventor Dilip Risbud
Dilip Risbud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735460Abstract: An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.Type: GrantFiled: July 28, 2021Date of Patent: August 22, 2023Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20210358795Abstract: An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 11164743Abstract: A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.Type: GrantFiled: January 14, 2020Date of Patent: November 2, 2021Assignee: QROMIS, INC.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 11107720Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: GrantFiled: December 5, 2019Date of Patent: August 31, 2021Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10755986Abstract: A substrate structure includes a polycrystalline substrate, a plurality of thin film layers disposed on the polycrystalline substrate, a bonding layer coupled to at least a portion of the plurality of thin films, and a single crystal silicon layer joined to the bonding layer.Type: GrantFiled: March 28, 2017Date of Patent: August 25, 2020Assignee: QROMIS, INC.Inventors: Ozgur Aktas, Vladimir Odnoblyudov, Dilip Risbud, Cem Basceri
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Publication number: 20200152456Abstract: A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.Type: ApplicationFiled: January 14, 2020Publication date: May 14, 2020Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20200111698Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10573516Abstract: A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.Type: GrantFiled: December 3, 2018Date of Patent: February 25, 2020Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10535547Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: GrantFiled: December 7, 2018Date of Patent: January 14, 2020Assignee: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10529613Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.Type: GrantFiled: July 1, 2019Date of Patent: January 7, 2020Assignee: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20190326148Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10395965Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.Type: GrantFiled: August 23, 2017Date of Patent: August 27, 2019Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20190172709Abstract: A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.Type: ApplicationFiled: December 3, 2018Publication date: June 6, 2019Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10290674Abstract: A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.Type: GrantFiled: April 19, 2017Date of Patent: May 14, 2019Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Cem Basceri
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Publication number: 20190122916Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: ApplicationFiled: December 7, 2018Publication date: April 25, 2019Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Patent number: 10204778Abstract: A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The method further includes forming a Schottky diode coupled to the engineered substrate. The Schottky diode has a top surface and a bottom surface. The bottom surface is coupled to the substantially single crystalline silicon layer. The method further includes forming a Schottky contact coupled to the top surface of the Schottky diode, forming a metal plating coupled to the Schottky contact, removing the engineered substrate to expose the bottom surface of the Schottky diode, and forming an ohmic contact on the bottom surface of the Schottky diode.Type: GrantFiled: December 19, 2017Date of Patent: February 12, 2019Assignee: Qromis, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas
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Patent number: 10181419Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: GrantFiled: August 23, 2017Date of Patent: January 15, 2019Assignee: QROMIS, INC.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20180182620Abstract: A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The method further includes forming a Schottky diode coupled to the engineered substrate. The Schottky diode has a top surface and a bottom surface. the bottom surface is coupled to the substantially single crystalline silicon layer. The method further includes forming a Schottky contact coupled to the top surface of the Schottky diode, forming a metal plating coupled to the Schottky contact, removing the engineered substrate to expose the bottom surface of the Schottky diode, and forming an ohmic contact on the bottom surface of the Schottky diode.Type: ApplicationFiled: December 19, 2017Publication date: June 28, 2018Applicant: QROMIS, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas
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Publication number: 20180061630Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.Type: ApplicationFiled: August 23, 2017Publication date: March 1, 2018Applicant: Quora Technology, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
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Publication number: 20180061694Abstract: A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.Type: ApplicationFiled: August 23, 2017Publication date: March 1, 2018Applicant: Quora Technology, Inc.Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri