Patents by Inventor Dimitri MAVROIDIS

Dimitri MAVROIDIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10637780
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 28, 2020
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Publication number: 20180198713
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Inventor: Dimitri MAVROIDIS
  • Patent number: 9893999
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 13, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Patent number: 9781039
    Abstract: Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 3, 2017
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Dimitri Mavroidis
  • Publication number: 20150163024
    Abstract: Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: Applied Micro Circuits Corporation
    Inventor: Dimitri MAVROIDIS
  • Publication number: 20150150009
    Abstract: Systems and methods for multi-channel signal processing by virtue of packet-based time-slicing with single processing core logic. The processing core logic is configured to receive data streams from the multiple communication channels at a data processing unit, and process data fragments of the data streams in a time-sliced manner. The processing core logic can switch from processing a first data fragment of a first data stream to processing a first data fragment of a second data stream at an end of a time slice, wherein the time slice is determined by a fragment boundary associated with the data fragment of the first data stream.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Applied Micro Circuits Corporation
    Inventor: Dimitri MAVROIDIS