Patents by Inventor Dimitrios CHATZISTRATIS

Dimitrios CHATZISTRATIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11921244
    Abstract: Some embodiments include an imaging system comprising a detector substrate, at least one detector circuit comprising a capacitor coupled with the detector substrate, the capacitor arranged to collect an electrical charge from the detector substrate, and the imaging system further comprises at least one programmable current source, arranged to provide a neutralizing charge to the capacitor, and the imaging system is configured to select a value for the neutralizing charge in dependence of a frame number.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: March 5, 2024
    Assignee: Oy Direct Conversion Ltd.
    Inventors: Tuomas Pantsar, Jouni Pyyhtiä, Dimitrios Chatzistratis, Gerasimos Theodoratos, Yannis Glikiotis, Teemu Pitkänen
  • Patent number: 11653886
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 23, 2023
    Assignee: ATHLOS OY
    Inventors: Konstantinos Spartiotis, Dimitrios Chatzistratis
  • Patent number: 11647972
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 16, 2023
    Assignee: ATHLOS OY
    Inventors: Konstantinos Spartiotis, Dimitrios Chatzistratis
  • Patent number: 11559267
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 24, 2023
    Assignee: ATHLOS OY
    Inventors: Konstantinos Spartiotis, Dimitrios Chatzistratis
  • Publication number: 20220395239
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 15, 2022
    Inventors: Konstantinos SPARTIOTIS, Dimitrios CHATZISTRATIS
  • Publication number: 20220395240
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 15, 2022
    Inventors: Konstantinos SPARTIOTIS, Dimitrios CHATZISTRATIS
  • Publication number: 20220018978
    Abstract: Some embodiments include an imaging system comprising a detector substrate, at least one detector circuit comprising a capacitor coupled with the detector substrate, the capacitor arranged to collect an electrical charge from the detector substrate, and the imaging system further comprises at least one programmable current source, arranged to provide a neutralizing charge to the capacitor, and the imaging system is configured to select a value for the neutralizing charge in dependence of a frame number.
    Type: Application
    Filed: November 28, 2019
    Publication date: January 20, 2022
    Applicant: OY AJAT LTD.
    Inventors: Tuomas Pantsar, Jouni Pyyhtiä, Dimitrios Chatzistratis, Gerasimos Theodoratos, Yannis Glikiotis, Teemu Pitkänen
  • Publication number: 20210022694
    Abstract: Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Inventors: Konstantinos SPARTIOTIS, Dimitrios CHATZISTRATIS